Manuals / PMC-Sierra / Computer Equipment / Network Router

PMC-Sierra PM5349 Serial to Parallel Converter, Receive Section Overhead Processor Rsop, Framer

Models: PM5349

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PMC-Sierra, Inc.

S/UNI-QUAD

DATASHEET

PM5349 S/UNI-QUAD

PMC-971239	ISSUE 6	SATURN USER NETWORK INTERFACE (155-QUAD)

Figure 2: Typical STS-3c (STM-1) Jitter Tolerance

100

10

GR-253-CORE

1

0.1
100	1000	10000	100000	1000000	10000000
		Jitter Freq. (Hz)

Note that for frequencies below 300 Hz, the jitter tolerance is greater than 15 UIpp; 15 UIpp is the maximum jitter tolerance of the test equipment. Also note that the dip in the tolerance curve between 300 Hz and 10 kHz is due to the S/UNI-QUAD's internal clock difference detector: if the recovered clock drifts beyond 488 ppm of the reference, the PLL locks to the reference clock.

10.1.2Serial to Parallel Converter

The Serial to Parallel Converter (SIPO) converts the received bit serial stream to a byte serial stream. The SIPO searches for the SONET/SDH framing pattern (A1, A2) in the receive stream, and performs serial to parallel conversion on octet boundaries.

10.2 Receive Section Overhead Processor (RSOP)

The Receive Section Overhead Processor (RSOP) provides frame synchronization, de-scrambling, section level alarm and performance monitoring.

10.2.1Framer

The Framer Block determines the in-frame/out-of-frame status of the receive stream.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

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PMC-Sierra PM5349 manual Serial to Parallel Converter, Receive Section Overhead Processor Rsop, Framer

Contents

UNI-QUAD Saturn User Network Interface Revision History Issue Issue Date Details of ChangeContents Receive Line Overhead Processor Rlop Transmit ATM Cell Processor Txcp Analog Power Supply Filtering Features GeneralSonet Receiver Sonet Transmitter Receive ATM ProcessorTransmit ATM Processor Applications References Definitions Application Examples Typical STS-3c STM-1 ATM Switch Port ApplicationCS B Block DiagramDescription PM5349 S/UNI-QUAD Bottom View PIN DiagramPIN Description Line Side Interface Signals Pin Name Type FunctionPin Name Type Function Tclk TfpiTDAT7 TfpoTDAT9 TDAT8Tsoc TprtyTADR2 TenbTADR4 TADR3Tfclk TCADTCA1 DTCA4DTCA3 DTCA2Rprty RsocRenb RADR1 RADR4RADR3 RADR2DRCA1 DRCA4DRCA3 DRCA2WRB Microprocessor Interface Signals Pin Name Type FunctionCSB RDBRstb ALEIntb Jtag Test Access Port TAP Signals Pin Name Type Function Power and Ground Pin Name Type Function Analog Signals Pin Name Type FunctionAC1 VDDAA3 AB2AC2 AC6 AC8 VSSAA2 AB1 AB3Qavs QavdAA6 QAVD1 QAVD2TAVS1B CSU AVSAC3 TAVS1A CSUTRSTB, TCK, TMS, TDI, TDO 5V tolerant I/O’sClock Recovery Functional DescriptionReceive Line Interface Crsi Serial to Parallel Converter Receive Section Overhead Processor RsopFramer Error Monitor Loss of SignalDescramble Line RDI Detect Error Monitor BlockLoss of Frame Receive Line Overhead Processor RlopPM5349 S/UNI-QUAD Synchronization Status Extraction Bit Error Rate MonitorPointer Interpreter Receive Path Overhead Processor RpopPointer Interpreter Event Indications Description LOP AISPM5349 S/UNI-QUAD Pointer Interpreter Transition Description SPE Timing Cell Delineation Receive ATM Cell Processor RxcpCell Filter and HCS Verification DescramblerHCS Verification State Diagram Performance Monitor Transmit Line Interface CspiClock Synthesis BIP-8 Insert Parallel to Serial ConverterTransmit Section Overhead Processor Tsop Line AIS InsertAPS Insert Framing and Identity InsertScrambler Transmit Line Overhead Processor TlopLine Febe Insert Transmit Path Overhead Processor TpopPointer Generator Idle/Unassigned Cell Generator BIP-8 CalculateFebe Calculate Transmit ATM Cell Processor TxcpTransmit ATM Interface HCS GeneratorUtopia Level 2 System Interface Receive ATM InterfaceJtag Test Access Port Microprocessor InterfaceRegister Memory Map REG Address A100 Description 363 Rxcp Interrupt Enables and Counter Status Tpop Path Signal LabelRxcp Configuration 362 Rxcp FIFO/UTOPIA Control & ConfigRxcp Idle Cell Count LSB 06F 16F 26F 36F Txcp ConfigurationTxcp Transmit Cell Status/Configuration Options Txcp Interrupt Enable/Status0FB 1FB 2FB 3FB 0EF 1EF 2EF 3EFRase APS K1 Rase APS K20FE 1FE 2FE 3FE UNI-QUAD Master Test RegisterReserved for Test Normal Mode Register Description TYPE1 ResetTYPE3 TYPE2Tfpo Channel Selection Bit ReservedTFPOCH1 TFPOCH0PM5349 S/UNI-QUAD Phyen PHYADR2PHYADR1 PHYADR0Refclka TclkaRfclka TfclkaRCLK4A RCLK1ARCLK2A RCLK3ACHNL2I CsuiCHNL4I CHNL3ICsui TIP ChresetAutoprdi AutopfebeAutolfebe AutolrdiSdle TfpienRxdinv LooptRxdinv PM5349 S/UNI-QUAD Rxcpi RaseiCrui TxcpiTxcpi Trooli TroolvTroole PM5349 S/UNI-QUAD Rdoolv RrooliRdooli RroolvRdooli PM5349 S/UNI-QUAD Bipee BipwordFoof ALGO2DDS Oofi BipeiLosi LofiBipei Bit Type Function Default Bit SBE7 SBE6 SBE5 SBE4 SBE3 SBE2 SBE1 SBE0Register 0x13 Rsop Section BIP-8 MSB Lais Register 0x14 Tsop Control Bit Type Function DefaultDFP Register 0x15 Tsop Diagnostic Bit Type Function DefaultDlos DBIP8Register 0x18 Rlop Control/Status Bit Type Function Default Lrdidet Laisi LaiseLrdie FebeiFebee Bit LBE7 LBE6 LBE5 LBE4 LBE3 LBE2 LBE1 LBE0 Register 0x1B Rlop Line BIP-24Bit LBE15 LBE14 LBE13 LBE12 LBE11 LBE10 LBE9 LBE8 Register 0x1C Rlop Line BIP-24 MSB Bit Type Function Default Bit LFE15 LFE14 LFE13 LFE12 LFE11 LFE10 LFE9 LFE8 Register 0x1D Rlop Line Febe LSB Bit Type Function DefaultBit LFE7 LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Register 0x1E Rlop Line FebeRegister 0x1F Rlop Line Febe MSB Bit Type Function Default Register 0x20 Tlop Control Bit Type Function Default ApsregLrdi Dbip Register 0x21 Tlop Diagnostic Bit Type Function DefaultRegister 0x22 Tlop Transmit K1 Bit Type Function Default Register 0x23 Tlop Transmit K2 Bit Type Function Default PM5349 S/UNI-QUAD Paisv LopconvLopv PaisonvPlopv PaisconvERDIV0 IinvcntERDIV2 ERDIV1Prdii PsliLopi Paisi104 Erdii Illptri IlljreqiDiscopai Invndfi107 Lope PaisePrdie Psle Erdie Illptre IlljreqeDiscopae Invndfe112 Register 0x35 Rpop Pointer LSB Bit Type Function Default Ndfpor ExtdRDI10 115 116 Register 0x38 Rpop Path BIP-8 LSB Bit Type Function Default Bit PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0Register 0x39 Rpop Path BIP-8 MSB Register 0x3A Rpop Path Febe LSB Bit Type Function Default Register 0x3B Rpop Path Febe MSB Bit Type Function DefaultBit PFE7 PFE6 PFE5 PFE4 PFE3 PFE2 PFE1 PFE0 Aprdiv Register 0x3C Rpop Auxiliary RDI Bit Type Function DefaultAprdie Aprdiv AprdieBlkbipo SOSEnss Blkbip121 Eprdien EprdisrcPersist 123 NDF FtptrNSE PSE125 CPTR4 CPTR7CPTR6 CPTR5CPTR8 CPTR9APTR4 APTR7APTR6 APTR5Bit NDF3 NDF2 NDF1 NDF0 APTR9APTR8 130 Register 0x49 Tpop Path Status Bit Type Function Default 132 Ddscr Register 0x60 Rxcp Configuration Bit Type Function DefaultDiscor HcsaddHCSFTR0 Register 0x61 Rxcp Configuration Bit Type Function DefaultCcdis HCSFTR1Hcspass Fiforst RCALEVEL0 RxptypRcainv Fiforst137 Fovre XferiOVR Xfere139 Fovri OocdiChcsi UhcsiOocdv LCDC6 LCDC9LCDC8 LCDC7CLP Bit GFC3 GFC2 GFC1 GFC0 PTI3 PTI2 PTI1MGFC0 MGFC3MGFC2 MGFC1CHCS4 CHCS7CHCS6 CHCS5UHCS4 UHCS7UHCS6 UHCS5RCELL4 RCELL7RCELL6 RCELL5148 ICELL4 ICELL7ICELL6 ICELL5ICELL18 ICELL17ICELL16 Hcsb Register 0x80 Txcp Configuration Bit Type Function DefaultTptyp DscrTCALEVEL0 Register 0x81 Txcp Configuration Bit Type Function Default FIFODP1 FIFODP0 Fifo Depth CellsCell H4INSB 156 Tsoci TprtyeTsoce Tprtyi158 Bit GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 PAYLD4 PAYLD7PAYLD6 PAYLD5Register 0x87 Txcp Transmit Cell Count 162 Loslrdi SdlrdiSflrdi Loflrdi164 Lopprdi LcdprdiAlrmprdi Paisprdi166 Pslmeprdi LcdeprdiNoalmeprdi Nopaiseprdi168 Nopaisconeprdi PaisconprdiLosins SdinsSfins Lofins171 Paispais PaisconpaisLopconpais LoppaisLopen PerdienPrdien PaisenAlarm Description Coapse Bit Z1/S1ESdbere SfbereSdberi PsbfiCoapsi Sfberi177 Sdcmode SfbertenSfsmode SdbertenSfcmode SFSAP4 SFSAP7SFSAP6 SFSAP5SFSAP20 SFSAP23SFSAP22 SFSAP21SFSTH4 SFSTH7SFSTH6 SFSTH5SFDTH4 SFDTH7SFDTH6 SFDTH5SFCTH4 SFCTH7SFCTH6 SFCTH5SDSAP4 SDSAP7SDSAP6 SDSAP5SDSAP20 SDSAP23SDSAP22 SDSAP21SDSTH4 SDSTH7SDSTH6 SDSTH5SDDTH4 SDDTH7SDDTH6 SDDTH5SDCTH4 SDCTH7SDCTH6 SDCTH5Register 0xF5 Rase Receive K1 Bit Type Function Default Register 0xF6 Rase Receive K2 Bit Type Function Default Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default Test Features Description Test Mode Register Memory Map AddressMaster Test Register Register 0x400 Master Test Bit Type Function Default Test Mode 0 Details Test Mode 0 Read LocationsPmcatst Boundary Scan 000 Test Mode 0 Write LocationsJtag Test Port ExtestInstructions Selected Register Instruction Codes IR20 Identification RegisterBoundary Scan Register Boundary Scan Cells Input PadMUX Bidirectional Cell Iocell Output Cell OutcellOutput Enable IocellPAD ATM Mapping into the STS-3c STM-1 SPE OperationTransport Overhead Bytes Transport and Path Overhead BytesPath Overhead Bytes PAYLOAD5 PAYLOAD6 ATM Cell Data StructurePAYLOAD1 PAYLOAD2 PAYLOAD3 PAYLOAD4205 Clocking Options Recommended Berm settingsConceptual Clocking Structure Loopback Operation Line Loopback Mode Serial Diagnostic Loopback Mode Parallel Diagnostic Loopback Mode Trstb TCK Control Select Tri-state EnableJtag Support TDO TMSTAP Controller TAP Controller Finite State Machine Capture-DR States Test-Logic-ResetUpdate-DR Run-Test-IdleBypass Update-IRShift-IR Boundary Scan InstructionsIdcode StctestBoard Design Recommendations Power Supply Sequencing Analog Power Supply Filtering Power Sequencing CircuitInterfacing to ECL or Pecl Devices LAN Mode Analog Power Filters with 3.3V SupplyInterfacing to ECL or Pecl Initializing the S/UNI-QUAD Using the S/UNI-QUAD with a 5 Volt ODLATM Utopia Level 2 System Interface Functional TimingMulti-PHY Polling and Addressing Receive Cell Interface 225 Absolute Maximum Ratings Absolute Maximum RatingsTBD 16 D.C. CharacteristicsInput High Current +10 VIH = VDD. Notes 2 Input Low Current 100 VIL = GND. Notes 1Input High Current +10 VIH = VDD. Notes 1 Input Low Current +10 VIL = GND. Notes 2Address to Latch Set-up Time Microprocessor Interface Timing CharacteristicsALE CSB+RDB Intb TSALW TSALW tHALW TV L TSAW tVWR tHAW ALE CSB+WRBRstb Pulse Width 100 18 A.C. Timing CharacteristicsTenb Hold time to Tfclk Tfclk Frequency MHzTfclk Duty Cycle Tenb Set-up time to TfclkTransmit ATM System Interface Timing Diagram Renb Hold time to Rfclk Rfclk Frequency MHzRfclk Duty Cycle Renb Set-up time to RfclkReceive ATM System Interface Timing Diagram RCLK1-4 High to RFPO1-4 Valid Tfpi Set-up Time to Tclk HighTfpi Hold Time to Tclk High Tclk High to Tfpo Valid239 Jtag Port Interface Timing 241 Theta Ja Theta Jc Ordering and Thermal InformationOrdering Information Thermal Information243 Mechanical Drawing 304 Pin Super Ball Grid Array Sbga Mechanical Information245 Web Site Contacting PMC-SIERRA, INCCorporate Information Application Information