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PMC-Sierra PM5349 manual Tprty, Tsoc

Models: PM5349

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		PMC-Sierra, Inc.	PM5349 S/UNI-QUAD
S/UNI-QUAD			PM5349 S/UNI-QUAD
S/UNI-QUAD
DATASHEET


PMC-971239	ISSUE 6		SATURN USER NETWORK INTERFACE (155-QUAD)

Pin Name	Type	Pin	Function
		No.

TPRTY	Input	H22	UTOPIA Transmit bus parity (TPRTY) signal.
			The transmit parity (TPRTY) signal indicates the
			parity of the TDAT[15:0] bus. A parity error is
			indicated by a status bit and a maskable interrupt.
			Cells with parity errors are inserted in the transmit
			stream, so the TPRTY input may be unused. Odd or
			even parity selection is made independently for
			each channel using the RXPTYP register bit.
			TPRTY is considered valid only when TENB is
			simultaneously asserted and the S/UNI-QUAD is
			selected via TADR[4:0].
			TPRTY is sampled on the rising edge of TFCLK.

TSOC	Input	J21	UTOPIA Transmit Start of Cell (TSOC) signal.
			The transmit start of cell (TSOC) signal marks the
			start of cell on the TDAT bus. When TSOC is high,
			the first word of the cell structure is present on the
			TDAT bus. It is not necessary for TSOC to be
			present for each cell. An interrupt may be
			generated if TSOC is high during any word other
			than the first word of the cell structure.
			TSOC is considered valid only when TENB is
			simultaneously asserted and the S/UNI-QUAD is
			selected via TADR[4:0].
			TSOC is sampled on the rising edge of TFCLK.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

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PMC-Sierra PM5349 manual Tprty, Tsoc

Contents

UNI-QUAD Saturn User Network Interface Issue Issue Date Details of Change Revision HistoryContents Receive Line Overhead Processor Rlop Transmit ATM Cell Processor Txcp Analog Power Supply Filtering General FeaturesSonet Receiver Receive ATM Processor Sonet TransmitterTransmit ATM Processor Applications References Definitions Typical STS-3c STM-1 ATM Switch Port Application Application ExamplesBlock Diagram CS BDescription PM5349 S/UNI-QUAD PIN Diagram Bottom ViewLine Side Interface Signals Pin Name Type Function PIN DescriptionPin Name Type Function Tfpi TclkTDAT8 TfpoTDAT9 TDAT7Tprty TsocTADR3 TenbTADR4 TADR2TCA TfclkDTCA2 DTCA4DTCA3 DTCA1Rsoc RprtyRenb RADR2 RADR4RADR3 RADR1DRCA2 DRCA4DRCA3 DRCA1RDB Microprocessor Interface Signals Pin Name Type FunctionCSB WRBALE RstbIntb Jtag Test Access Port TAP Signals Pin Name Type Function Analog Signals Pin Name Type Function Power and Ground Pin Name Type FunctionAB2 VDDAA3 AC1AB1 AB3 VSSAA2 AC2 AC6 AC8QAVD2 QavdAA6 QAVD1 QavsTAVS1A CSU AVSAC3 TAVS1B CSU5V tolerant I/O’s TRSTB, TCK, TMS, TDI, TDOFunctional Description Clock RecoveryReceive Line Interface Crsi Receive Section Overhead Processor Rsop Serial to Parallel ConverterFramer Loss of Signal Error MonitorDescramble Receive Line Overhead Processor Rlop Error Monitor BlockLoss of Frame Line RDI DetectPM5349 S/UNI-QUAD Bit Error Rate Monitor Synchronization Status ExtractionReceive Path Overhead Processor Rpop Pointer InterpreterLOP AIS Pointer Interpreter Event Indications DescriptionPM5349 S/UNI-QUAD Pointer Interpreter Transition Description SPE Timing Receive ATM Cell Processor Rxcp Cell DelineationDescrambler Cell Filter and HCS VerificationHCS Verification State Diagram Transmit Line Interface Cspi Performance MonitorClock Synthesis Line AIS Insert Parallel to Serial ConverterTransmit Section Overhead Processor Tsop BIP-8 InsertTransmit Line Overhead Processor Tlop Framing and Identity InsertScrambler APS InsertTransmit Path Overhead Processor Tpop Line Febe InsertPointer Generator Transmit ATM Cell Processor Txcp BIP-8 CalculateFebe Calculate Idle/Unassigned Cell GeneratorReceive ATM Interface HCS GeneratorUtopia Level 2 System Interface Transmit ATM InterfaceMicroprocessor Interface Jtag Test Access PortRegister Memory Map REG Address A100 Description 362 Rxcp FIFO/UTOPIA Control & Config Tpop Path Signal LabelRxcp Configuration 363 Rxcp Interrupt Enables and Counter StatusTxcp Interrupt Enable/Status Txcp ConfigurationTxcp Transmit Cell Status/Configuration Options Rxcp Idle Cell Count LSB 06F 16F 26F 36FRase APS K2 0EF 1EF 2EF 3EFRase APS K1 0FB 1FB 2FB 3FBUNI-QUAD Master Test Register 0FE 1FE 2FE 3FEReserved for Test Normal Mode Register Description TYPE2 ResetTYPE3 TYPE1TFPOCH0 Bit ReservedTFPOCH1 Tfpo Channel SelectionPM5349 S/UNI-QUAD PHYADR0 PHYADR2PHYADR1 PhyenTfclka TclkaRfclka RefclkaRCLK3A RCLK1ARCLK2A RCLK4ACHNL3I CsuiCHNL4I CHNL2ICsui Chreset TIPAutolrdi AutopfebeAutolfebe AutoprdiLoopt TfpienRxdinv SdleRxdinv PM5349 S/UNI-QUAD Txcpi RaseiCrui RxcpiTxcpi Troolv TrooliTroole PM5349 S/UNI-QUAD Rroolv RrooliRdooli RdoolvRdooli PM5349 S/UNI-QUAD ALGO2 BipwordFoof BipeeDDS Lofi BipeiLosi OofiBipei Bit SBE7 SBE6 SBE5 SBE4 SBE3 SBE2 SBE1 SBE0 Bit Type Function DefaultRegister 0x13 Rsop Section BIP-8 MSB Register 0x14 Tsop Control Bit Type Function Default LaisDBIP8 Register 0x15 Tsop Diagnostic Bit Type Function DefaultDlos DFPRegister 0x18 Rlop Control/Status Bit Type Function Default Lrdidet Febei LaiseLrdie LaisiFebee Register 0x1B Rlop Line BIP-24 Bit LBE7 LBE6 LBE5 LBE4 LBE3 LBE2 LBE1 LBE0Bit LBE15 LBE14 LBE13 LBE12 LBE11 LBE10 LBE9 LBE8 Register 0x1C Rlop Line BIP-24 MSB Bit Type Function Default Register 0x1E Rlop Line Febe Register 0x1D Rlop Line Febe LSB Bit Type Function DefaultBit LFE7 LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Bit LFE15 LFE14 LFE13 LFE12 LFE11 LFE10 LFE9 LFE8Register 0x1F Rlop Line Febe MSB Bit Type Function Default Apsreg Register 0x20 Tlop Control Bit Type Function DefaultLrdi Register 0x21 Tlop Diagnostic Bit Type Function Default DbipRegister 0x22 Tlop Transmit K1 Bit Type Function Default Register 0x23 Tlop Transmit K2 Bit Type Function Default PM5349 S/UNI-QUAD Paisonv LopconvLopv PaisvPaisconv PlopvERDIV1 IinvcntERDIV2 ERDIV0Paisi PsliLopi Prdii104 Erdii Invndfi IlljreqiDiscopai Illptri107 Paise LopePrdie Psle Erdie Invndfe IlljreqeDiscopae Illptre112 Register 0x35 Rpop Pointer LSB Bit Type Function Default Extd NdfporRDI10 115 116 Bit PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0 Register 0x38 Rpop Path BIP-8 LSB Bit Type Function DefaultRegister 0x39 Rpop Path BIP-8 MSB Register 0x3B Rpop Path Febe MSB Bit Type Function Default Register 0x3A Rpop Path Febe LSB Bit Type Function DefaultBit PFE7 PFE6 PFE5 PFE4 PFE3 PFE2 PFE1 PFE0 Aprdiv Aprdie Register 0x3C Rpop Auxiliary RDI Bit Type Function DefaultAprdie AprdivBlkbip SOSEnss Blkbipo121 Eprdisrc EprdienPersist 123 PSE FtptrNSE NDF125 CPTR5 CPTR7CPTR6 CPTR4CPTR9 CPTR8APTR5 APTR7APTR6 APTR4APTR9 Bit NDF3 NDF2 NDF1 NDF0APTR8 130 Register 0x49 Tpop Path Status Bit Type Function Default 132 Hcsadd Register 0x60 Rxcp Configuration Bit Type Function DefaultDiscor DdscrHCSFTR1 Register 0x61 Rxcp Configuration Bit Type Function DefaultCcdis HCSFTR0Hcspass Fiforst RxptypRcainv Fiforst RCALEVEL0137 Xfere XferiOVR Fovre139 Uhcsi OocdiChcsi FovriOocdv LCDC7 LCDC9LCDC8 LCDC6Bit GFC3 GFC2 GFC1 GFC0 PTI3 PTI2 PTI1 CLPMGFC1 MGFC3MGFC2 MGFC0CHCS5 CHCS7CHCS6 CHCS4UHCS5 UHCS7UHCS6 UHCS4RCELL5 RCELL7RCELL6 RCELL4148 ICELL5 ICELL7ICELL6 ICELL4ICELL17 ICELL18ICELL16 Dscr Register 0x80 Txcp Configuration Bit Type Function DefaultTptyp HcsbTCALEVEL0 Register 0x81 Txcp Configuration Bit Type Function Default Cells FIFODP1 FIFODP0 Fifo DepthCell H4INSB 156 Tprtyi TprtyeTsoce Tsoci158 Bit GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 PAYLD5 PAYLD7PAYLD6 PAYLD4Register 0x87 Txcp Transmit Cell Count 162 Loflrdi SdlrdiSflrdi Loslrdi164 Paisprdi LcdprdiAlrmprdi Lopprdi166 Nopaiseprdi LcdeprdiNoalmeprdi Pslmeprdi168 Paisconprdi NopaisconeprdiLofins SdinsSfins Losins171 Loppais PaisconpaisLopconpais PaispaisPaisen PerdienPrdien LopenAlarm Description Sfbere Bit Z1/S1ESdbere CoapseSfberi PsbfiCoapsi Sdberi177 Sdberten SfbertenSfsmode SdcmodeSfcmode SFSAP5 SFSAP7SFSAP6 SFSAP4SFSAP21 SFSAP23SFSAP22 SFSAP20SFSTH5 SFSTH7SFSTH6 SFSTH4SFDTH5 SFDTH7SFDTH6 SFDTH4SFCTH5 SFCTH7SFCTH6 SFCTH4SDSAP5 SDSAP7SDSAP6 SDSAP4SDSAP21 SDSAP23SDSAP22 SDSAP20SDSTH5 SDSTH7SDSTH6 SDSTH4SDDTH5 SDDTH7SDDTH6 SDDTH4SDCTH5 SDCTH7SDCTH6 SDCTH4Register 0xF5 Rase Receive K1 Bit Type Function Default Register 0xF6 Rase Receive K2 Bit Type Function Default Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default Test Mode Register Memory Map Address Test Features DescriptionMaster Test Register Register 0x400 Master Test Bit Type Function Default Test Mode 0 Read Locations Test Mode 0 DetailsPmcatst Extest Test Mode 0 Write LocationsJtag Test Port Boundary Scan 000Identification Register Instructions Selected Register Instruction Codes IR20Boundary Scan Register Input Pad Boundary Scan CellsMUX Output Cell Outcell Bidirectional Cell IocellIocell Output EnablePAD Operation ATM Mapping into the STS-3c STM-1 SPETransport and Path Overhead Bytes Transport Overhead BytesPath Overhead Bytes PAYLOAD3 PAYLOAD4 ATM Cell Data StructurePAYLOAD1 PAYLOAD2 PAYLOAD5 PAYLOAD6205 Recommended Berm settings Clocking OptionsConceptual Clocking Structure Loopback Operation Line Loopback Mode Serial Diagnostic Loopback Mode Parallel Diagnostic Loopback Mode TDO TMS Control Select Tri-state EnableJtag Support Trstb TCKTAP Controller TAP Controller Finite State Machine Run-Test-Idle States Test-Logic-ResetUpdate-DR Capture-DRBoundary Scan Instructions Update-IRShift-IR BypassStctest IdcodeBoard Design Recommendations Power Supply Sequencing Power Sequencing Circuit Analog Power Supply FilteringLAN Mode Analog Power Filters with 3.3V Supply Interfacing to ECL or Pecl DevicesInterfacing to ECL or Pecl Using the S/UNI-QUAD with a 5 Volt ODL Initializing the S/UNI-QUADFunctional Timing ATM Utopia Level 2 System InterfaceMulti-PHY Polling and Addressing Receive Cell Interface 225 Absolute Maximum Ratings Absolute Maximum Ratings16 D.C. Characteristics TBDInput Low Current +10 VIL = GND. Notes 2 Input Low Current 100 VIL = GND. Notes 1Input High Current +10 VIH = VDD. Notes 1 Input High Current +10 VIH = VDD. Notes 2Microprocessor Interface Timing Characteristics Address to Latch Set-up TimeALE CSB+RDB Intb TSALW ALE CSB+WRB TSALW tHALW TV L TSAW tVWR tHAW18 A.C. Timing Characteristics Rstb Pulse Width 100Tenb Set-up time to Tfclk Tfclk Frequency MHzTfclk Duty Cycle Tenb Hold time to TfclkTransmit ATM System Interface Timing Diagram Renb Set-up time to Rfclk Rfclk Frequency MHzRfclk Duty Cycle Renb Hold time to RfclkReceive ATM System Interface Timing Diagram Tclk High to Tfpo Valid Tfpi Set-up Time to Tclk HighTfpi Hold Time to Tclk High RCLK1-4 High to RFPO1-4 Valid239 Jtag Port Interface Timing 241 Thermal Information Ordering and Thermal InformationOrdering Information Theta Ja Theta Jc243 Mechanical Information Mechanical Drawing 304 Pin Super Ball Grid Array Sbga245 Application Information Contacting PMC-SIERRA, INCCorporate Information Web Site