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PMC-Sierra PM5349 manual Transmit ATM Cell Processor Txcp

Models: PM5349

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					PMC-Sierra, Inc.	PM5349 S/UNI-QUAD
S/UNI-QUAD						PM5349 S/UNI-QUAD
S/UNI-QUAD
DATASHEET


PMC-971239				ISSUE 6	SATURN USER NETWORK INTERFACE (155-QUAD)

		10.10.1		POINTER GENERATOR			49
		10.10.2		BIP-8 CALCULATE			50
		10.10.3		FEBE CALCULATE			50
	10.11	TRANSMIT ATM CELL PROCESSOR (TXCP)					50
		10.11.1		IDLE/UNASSIGNED CELL GENERATOR			50
		10.11.2		SCRAMBLER			50
		10.11.3		HCS GENERATOR			51
	10.12	UTOPIA LEVEL 2 SYSTEM INTERFACE					51
		10.12.1		RECEIVE ATM INTERFACE			51
		10.12.2		TRANSMIT ATM INTERFACE			51
	10.13	JTAG TEST ACCESS PORT					52
	10.14	MICROPROCESSOR INTERFACE					52
11	NORMAL MODE REGISTER DESCRIPTION						59
12	TEST FEATURES DESCRIPTION						193
	12.1	MASTER TEST REGISTER					193
	12.2	TEST MODE 0 DETAILS					195
	12.3	JTAG TEST PORT			............................................................................................		196
		12.3.1		BOUNDARY SCAN CELLS			198
13	OPERATION						201
	13.1	SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE					201
		13.1.1		ATM MAPPING			201
		13.1.2		TRANSPORT AND PATH OVERHEAD BYTES			202
	13.2	ATM CELL DATA STRUCTURE					204
	13.3	BIT ERROR RATE MONITOR					205
	13.4	CLOCKING OPTIONS					206
	13.5	LOOPBACK OPERATION					208
	13.6	JTAG SUPPORT					212
		13.6.1		TAP CONTROLLER			213
			13.6.1.1		STATES		215
			13.6.1.2		INSTRUCTIONS		216
	13.7	BOARD DESIGN RECOMMENDATIONS					217
	13.8	POWER SUPPLY SEQUENCING					218

Proprietary and Confidential to PMC-SIERRA, Inc., and for its Customers’ Internal Use

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PMC-Sierra PM5349 manual Transmit ATM Cell Processor Txcp

Contents

UNI-QUAD Saturn User Network Interface Revision History Issue Issue Date Details of ChangeContents Receive Line Overhead Processor Rlop Transmit ATM Cell Processor Txcp Analog Power Supply Filtering Sonet Receiver FeaturesGeneral Sonet Transmitter Receive ATM ProcessorTransmit ATM Processor Applications References Definitions Application Examples Typical STS-3c STM-1 ATM Switch Port ApplicationCS B Block DiagramDescription PM5349 S/UNI-QUAD Bottom View PIN DiagramPIN Description Line Side Interface Signals Pin Name Type FunctionPin Name Type Function Tclk TfpiTDAT9 TfpoTDAT8 TDAT7Tsoc TprtyTADR4 TenbTADR3 TADR2Tfclk TCADTCA3 DTCA4DTCA2 DTCA1Renb RprtyRsoc RADR3 RADR4RADR2 RADR1DRCA3 DRCA4DRCA2 DRCA1CSB Microprocessor Interface Signals Pin Name Type FunctionRDB WRBIntb RstbALE Jtag Test Access Port TAP Signals Pin Name Type Function Power and Ground Pin Name Type Function Analog Signals Pin Name Type FunctionAA3 VDDAB2 AC1AA2 VSSAB1 AB3 AC2 AC6 AC8AA6 QAVD1 QavdQAVD2 QavsAC3 AVSTAVS1A CSU TAVS1B CSUTRSTB, TCK, TMS, TDI, TDO 5V tolerant I/O’sReceive Line Interface Crsi Clock RecoveryFunctional Description Framer Serial to Parallel ConverterReceive Section Overhead Processor Rsop Descramble Error MonitorLoss of Signal Loss of Frame Error Monitor BlockReceive Line Overhead Processor Rlop Line RDI DetectPM5349 S/UNI-QUAD Synchronization Status Extraction Bit Error Rate MonitorPointer Interpreter Receive Path Overhead Processor RpopPointer Interpreter Event Indications Description LOP AISPM5349 S/UNI-QUAD Pointer Interpreter Transition Description SPE Timing Cell Delineation Receive ATM Cell Processor RxcpCell Filter and HCS Verification DescramblerHCS Verification State Diagram Clock Synthesis Performance MonitorTransmit Line Interface Cspi Transmit Section Overhead Processor Tsop Parallel to Serial ConverterLine AIS Insert BIP-8 InsertScrambler Framing and Identity InsertTransmit Line Overhead Processor Tlop APS InsertPointer Generator Line Febe InsertTransmit Path Overhead Processor Tpop Febe Calculate BIP-8 CalculateTransmit ATM Cell Processor Txcp Idle/Unassigned Cell GeneratorUtopia Level 2 System Interface HCS GeneratorReceive ATM Interface Transmit ATM InterfaceRegister Memory Map Jtag Test Access PortMicroprocessor Interface REG Address A100 Description Rxcp Configuration Tpop Path Signal Label362 Rxcp FIFO/UTOPIA Control & Config 363 Rxcp Interrupt Enables and Counter StatusTxcp Transmit Cell Status/Configuration Options Txcp ConfigurationTxcp Interrupt Enable/Status Rxcp Idle Cell Count LSB 06F 16F 26F 36FRase APS K1 0EF 1EF 2EF 3EFRase APS K2 0FB 1FB 2FB 3FBReserved for Test 0FE 1FE 2FE 3FEUNI-QUAD Master Test Register Normal Mode Register Description TYPE3 ResetTYPE2 TYPE1TFPOCH1 Bit ReservedTFPOCH0 Tfpo Channel SelectionPM5349 S/UNI-QUAD PHYADR1 PHYADR2PHYADR0 PhyenRfclka TclkaTfclka RefclkaRCLK2A RCLK1ARCLK3A RCLK4ACHNL4I CsuiCHNL3I CHNL2ICsui TIP ChresetAutolfebe AutopfebeAutolrdi AutoprdiRxdinv TfpienLoopt SdleRxdinv PM5349 S/UNI-QUAD Crui RaseiTxcpi RxcpiTxcpi Troole TrooliTroolv PM5349 S/UNI-QUAD Rdooli RrooliRroolv RdoolvRdooli PM5349 S/UNI-QUAD Foof BipwordALGO2 BipeeDDS Losi BipeiLofi OofiBipei Register 0x13 Rsop Section BIP-8 MSB Bit Type Function DefaultBit SBE7 SBE6 SBE5 SBE4 SBE3 SBE2 SBE1 SBE0 Lais Register 0x14 Tsop Control Bit Type Function DefaultDlos Register 0x15 Tsop Diagnostic Bit Type Function DefaultDBIP8 DFPRegister 0x18 Rlop Control/Status Bit Type Function Default Lrdidet Lrdie LaiseFebei LaisiFebee Bit LBE15 LBE14 LBE13 LBE12 LBE11 LBE10 LBE9 LBE8 Bit LBE7 LBE6 LBE5 LBE4 LBE3 LBE2 LBE1 LBE0Register 0x1B Rlop Line BIP-24 Register 0x1C Rlop Line BIP-24 MSB Bit Type Function Default Bit LFE7 LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Register 0x1D Rlop Line Febe LSB Bit Type Function DefaultRegister 0x1E Rlop Line Febe Bit LFE15 LFE14 LFE13 LFE12 LFE11 LFE10 LFE9 LFE8Register 0x1F Rlop Line Febe MSB Bit Type Function Default Lrdi Register 0x20 Tlop Control Bit Type Function DefaultApsreg Dbip Register 0x21 Tlop Diagnostic Bit Type Function DefaultRegister 0x22 Tlop Transmit K1 Bit Type Function Default Register 0x23 Tlop Transmit K2 Bit Type Function Default PM5349 S/UNI-QUAD Lopv LopconvPaisonv PaisvPlopv PaisconvERDIV2 IinvcntERDIV1 ERDIV0Lopi PsliPaisi Prdii104 Erdii Discopai IlljreqiInvndfi Illptri107 Prdie LopePaise Psle Erdie Discopae IlljreqeInvndfe Illptre112 Register 0x35 Rpop Pointer LSB Bit Type Function Default RDI10 NdfporExtd 115 116 Register 0x39 Rpop Path BIP-8 MSB Register 0x38 Rpop Path BIP-8 LSB Bit Type Function DefaultBit PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0 Bit PFE7 PFE6 PFE5 PFE4 PFE3 PFE2 PFE1 PFE0 Register 0x3A Rpop Path Febe LSB Bit Type Function DefaultRegister 0x3B Rpop Path Febe MSB Bit Type Function Default Aprdie Register 0x3C Rpop Auxiliary RDI Bit Type Function DefaultAprdiv Aprdie AprdivEnss SOSBlkbip Blkbipo121 Persist EprdienEprdisrc 123 NSE FtptrPSE NDF125 CPTR6 CPTR7CPTR5 CPTR4CPTR8 CPTR9APTR6 APTR7APTR5 APTR4APTR8 Bit NDF3 NDF2 NDF1 NDF0APTR9 130 Register 0x49 Tpop Path Status Bit Type Function Default 132 Discor Register 0x60 Rxcp Configuration Bit Type Function DefaultHcsadd DdscrCcdis Register 0x61 Rxcp Configuration Bit Type Function DefaultHCSFTR1 HCSFTR0Hcspass Rcainv RxptypFiforst Fiforst RCALEVEL0137 OVR XferiXfere Fovre139 Chcsi OocdiUhcsi FovriOocdv LCDC8 LCDC9LCDC7 LCDC6CLP Bit GFC3 GFC2 GFC1 GFC0 PTI3 PTI2 PTI1MGFC2 MGFC3MGFC1 MGFC0CHCS6 CHCS7CHCS5 CHCS4UHCS6 UHCS7UHCS5 UHCS4RCELL6 RCELL7RCELL5 RCELL4148 ICELL6 ICELL7ICELL5 ICELL4ICELL16 ICELL18ICELL17 Tptyp Register 0x80 Txcp Configuration Bit Type Function DefaultDscr HcsbTCALEVEL0 Register 0x81 Txcp Configuration Bit Type Function Default Cell FIFODP1 FIFODP0 Fifo DepthCells H4INSB 156 Tsoce TprtyeTprtyi Tsoci158 Bit GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 PAYLD6 PAYLD7PAYLD5 PAYLD4Register 0x87 Txcp Transmit Cell Count 162 Sflrdi SdlrdiLoflrdi Loslrdi164 Alrmprdi LcdprdiPaisprdi Lopprdi166 Noalmeprdi LcdeprdiNopaiseprdi Pslmeprdi168 Nopaisconeprdi PaisconprdiSfins SdinsLofins Losins171 Lopconpais PaisconpaisLoppais PaispaisPrdien PerdienPaisen LopenAlarm Description Sdbere Bit Z1/S1ESfbere CoapseCoapsi PsbfiSfberi Sdberi177 Sfsmode SfbertenSdberten SdcmodeSfcmode SFSAP6 SFSAP7SFSAP5 SFSAP4SFSAP22 SFSAP23SFSAP21 SFSAP20SFSTH6 SFSTH7SFSTH5 SFSTH4SFDTH6 SFDTH7SFDTH5 SFDTH4SFCTH6 SFCTH7SFCTH5 SFCTH4SDSAP6 SDSAP7SDSAP5 SDSAP4SDSAP22 SDSAP23SDSAP21 SDSAP20SDSTH6 SDSTH7SDSTH5 SDSTH4SDDTH6 SDDTH7SDDTH5 SDDTH4SDCTH6 SDCTH7SDCTH5 SDCTH4Register 0xF5 Rase Receive K1 Bit Type Function Default Register 0xF6 Rase Receive K2 Bit Type Function Default Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default Master Test Register Test Features DescriptionTest Mode Register Memory Map Address Register 0x400 Master Test Bit Type Function Default Pmcatst Test Mode 0 DetailsTest Mode 0 Read Locations Jtag Test Port Test Mode 0 Write LocationsExtest Boundary Scan 000Boundary Scan Register Instructions Selected Register Instruction Codes IR20Identification Register MUX Boundary Scan CellsInput Pad Bidirectional Cell Iocell Output Cell OutcellPAD Output EnableIocell ATM Mapping into the STS-3c STM-1 SPE OperationTransport Overhead Bytes Transport and Path Overhead BytesPath Overhead Bytes PAYLOAD1 PAYLOAD2 ATM Cell Data StructurePAYLOAD3 PAYLOAD4 PAYLOAD5 PAYLOAD6205 Clocking Options Recommended Berm settingsConceptual Clocking Structure Loopback Operation Line Loopback Mode Serial Diagnostic Loopback Mode Parallel Diagnostic Loopback Mode Jtag Support Control Select Tri-state EnableTDO TMS Trstb TCKTAP Controller TAP Controller Finite State Machine Update-DR States Test-Logic-ResetRun-Test-Idle Capture-DRShift-IR Update-IRBoundary Scan Instructions BypassBoard Design Recommendations IdcodeStctest Power Supply Sequencing Analog Power Supply Filtering Power Sequencing CircuitInterfacing to ECL or Pecl Devices LAN Mode Analog Power Filters with 3.3V SupplyInterfacing to ECL or Pecl Initializing the S/UNI-QUAD Using the S/UNI-QUAD with a 5 Volt ODLATM Utopia Level 2 System Interface Functional TimingMulti-PHY Polling and Addressing Receive Cell Interface 225 Absolute Maximum Ratings Absolute Maximum RatingsTBD 16 D.C. CharacteristicsInput High Current +10 VIH = VDD. Notes 1 Input Low Current 100 VIL = GND. Notes 1Input Low Current +10 VIL = GND. Notes 2 Input High Current +10 VIH = VDD. Notes 2Address to Latch Set-up Time Microprocessor Interface Timing CharacteristicsALE CSB+RDB Intb TSALW TSALW tHALW TV L TSAW tVWR tHAW ALE CSB+WRBRstb Pulse Width 100 18 A.C. Timing CharacteristicsTfclk Duty Cycle Tfclk Frequency MHzTenb Set-up time to Tfclk Tenb Hold time to TfclkTransmit ATM System Interface Timing Diagram Rfclk Duty Cycle Rfclk Frequency MHzRenb Set-up time to Rfclk Renb Hold time to RfclkReceive ATM System Interface Timing Diagram Tfpi Hold Time to Tclk High Tfpi Set-up Time to Tclk HighTclk High to Tfpo Valid RCLK1-4 High to RFPO1-4 Valid239 Jtag Port Interface Timing 241 Ordering Information Ordering and Thermal InformationThermal Information Theta Ja Theta Jc243 Mechanical Drawing 304 Pin Super Ball Grid Array Sbga Mechanical Information245 Corporate Information Contacting PMC-SIERRA, INCApplication Information Web Site