Initializing the S/UNI-QUAD | PMC-Sierra PM5349 specs

PMC-Sierra, Inc.

S/UNI-QUAD

DATASHEET

PM5349 S/UNI-QUAD

PMC-971239	ISSUE 6	SATURN USER NETWORK INTERFACE (155-QUAD)

13.11Initializing the S/UNI-QUAD

The S/UNI-QUAD defaults to the Asynchronous Transfer Mode (ATM) operation but it is recommended to implement the following initialization sequence.

1.Reset the device. This can be done by asserting the RSTB pin or setting the RESET bit in the Master Reset and ID Register (Register 00).

2.Set the TPOP Path Signal Label (Register 0x48 ) to 0x13, which indicates an ATM payload.

3.For every channel, reset all the Rx and Tx ATM FIFO’s by setting the

FIFORST register bit in the TXCP and RXCP blocks. Keep this bit set for at least 1 μs, then set the bit back to its inactive logic zero value.

4.For every channel, reset the performance monitoring counters in TXCP and RXCP blocks, and preferably in all the blocks. The easiest way to do this is to use the TIP register bit.

13.12Using the S/UNI-QUAD with a 5 Volt ODL

The S/UNI-QUAD defaults to a 3.3V PECL optical data link (ODL) module interface. It can also be used with a 5V ODL. This is accomplished by setting to logic 1 the PECLV bit located in the Master Configuration Register (Register 0x01). Notice that all four channels are reconfigured.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

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PMC-Sierra PM5349 manual Initializing the S/UNI-QUAD, Using the S/UNI-QUAD with a 5 Volt ODL

Contents

UNI-QUAD Saturn User Network Interface Issue Issue Date Details of Change Revision History Contents Receive Line Overhead Processor Rlop Transmit ATM Cell Processor Txcp Analog Power Supply Filtering Features GeneralSonet Receiver Receive ATM Processor Sonet Transmitter Transmit ATM Processor Applications References Definitions Typical STS-3c STM-1 ATM Switch Port Application Application Examples Block Diagram CS B Description PM5349 S/UNI-QUAD PIN Diagram Bottom View Line Side Interface Signals Pin Name Type Function PIN Description Pin Name Type Function Tfpi Tclk Tfpo TDAT9TDAT8 TDAT7 Tprty Tsoc Tenb TADR4TADR3 TADR2 TCA Tfclk DTCA4 DTCA3DTCA2 DTCA1 Rprty RsocRenb RADR4 RADR3RADR2 RADR1 DRCA4 DRCA3DRCA2 DRCA1 Microprocessor Interface Signals Pin Name Type Function CSBRDB WRB Rstb ALEIntb Jtag Test Access Port TAP Signals Pin Name Type Function Analog Signals Pin Name Type Function Power and Ground Pin Name Type Function VDD AA3AB2 AC1 VSS AA2AB1 AB3 AC2 AC6 AC8 Qavd AA6 QAVD1QAVD2 Qavs AVS AC3TAVS1A CSU TAVS1B CSU 5V tolerant I/O’s TRSTB, TCK, TMS, TDI, TDO Clock Recovery Functional DescriptionReceive Line Interface Crsi Serial to Parallel Converter Receive Section Overhead Processor RsopFramer Error Monitor Loss of SignalDescramble Error Monitor Block Loss of FrameReceive Line Overhead Processor Rlop Line RDI Detect PM5349 S/UNI-QUAD Bit Error Rate Monitor Synchronization Status Extraction Receive Path Overhead Processor Rpop Pointer Interpreter LOP AIS Pointer Interpreter Event Indications Description PM5349 S/UNI-QUAD Pointer Interpreter Transition Description SPE Timing Receive ATM Cell Processor Rxcp Cell Delineation Descrambler Cell Filter and HCS Verification HCS Verification State Diagram Performance Monitor Transmit Line Interface CspiClock Synthesis Parallel to Serial Converter Transmit Section Overhead Processor TsopLine AIS Insert BIP-8 Insert Framing and Identity Insert ScramblerTransmit Line Overhead Processor Tlop APS Insert Line Febe Insert Transmit Path Overhead Processor TpopPointer Generator BIP-8 Calculate Febe CalculateTransmit ATM Cell Processor Txcp Idle/Unassigned Cell Generator HCS Generator Utopia Level 2 System InterfaceReceive ATM Interface Transmit ATM Interface Jtag Test Access Port Microprocessor InterfaceRegister Memory Map REG Address A100 Description Tpop Path Signal Label Rxcp Configuration362 Rxcp FIFO/UTOPIA Control & Config 363 Rxcp Interrupt Enables and Counter Status Txcp Configuration Txcp Transmit Cell Status/Configuration OptionsTxcp Interrupt Enable/Status Rxcp Idle Cell Count LSB 06F 16F 26F 36F 0EF 1EF 2EF 3EF Rase APS K1Rase APS K2 0FB 1FB 2FB 3FB 0FE 1FE 2FE 3FE UNI-QUAD Master Test RegisterReserved for Test Normal Mode Register Description Reset TYPE3TYPE2 TYPE1 Bit Reserved TFPOCH1TFPOCH0 Tfpo Channel Selection PM5349 S/UNI-QUAD PHYADR2 PHYADR1PHYADR0 Phyen Tclka RfclkaTfclka Refclka RCLK1A RCLK2ARCLK3A RCLK4A Csui CHNL4ICHNL3I CHNL2I Csui Chreset TIP Autopfebe AutolfebeAutolrdi Autoprdi Tfpien RxdinvLoopt Sdle Rxdinv PM5349 S/UNI-QUAD Rasei CruiTxcpi Rxcpi Txcpi Trooli TroolvTroole PM5349 S/UNI-QUAD Rrooli RdooliRroolv Rdoolv Rdooli PM5349 S/UNI-QUAD Bipword FoofALGO2 Bipee DDS Bipei LosiLofi Oofi Bipei Bit Type Function Default Bit SBE7 SBE6 SBE5 SBE4 SBE3 SBE2 SBE1 SBE0Register 0x13 Rsop Section BIP-8 MSB Register 0x14 Tsop Control Bit Type Function Default Lais Register 0x15 Tsop Diagnostic Bit Type Function Default DlosDBIP8 DFP Register 0x18 Rlop Control/Status Bit Type Function Default Lrdidet Laise LrdieFebei Laisi Febee Bit LBE7 LBE6 LBE5 LBE4 LBE3 LBE2 LBE1 LBE0 Register 0x1B Rlop Line BIP-24Bit LBE15 LBE14 LBE13 LBE12 LBE11 LBE10 LBE9 LBE8 Register 0x1C Rlop Line BIP-24 MSB Bit Type Function Default Register 0x1D Rlop Line Febe LSB Bit Type Function Default Bit LFE7 LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0Register 0x1E Rlop Line Febe Bit LFE15 LFE14 LFE13 LFE12 LFE11 LFE10 LFE9 LFE8 Register 0x1F Rlop Line Febe MSB Bit Type Function Default Register 0x20 Tlop Control Bit Type Function Default ApsregLrdi Register 0x21 Tlop Diagnostic Bit Type Function Default Dbip Register 0x22 Tlop Transmit K1 Bit Type Function Default Register 0x23 Tlop Transmit K2 Bit Type Function Default PM5349 S/UNI-QUAD Lopconv LopvPaisonv Paisv Paisconv Plopv Iinvcnt ERDIV2ERDIV1 ERDIV0 Psli LopiPaisi Prdii 104 Erdii Illjreqi DiscopaiInvndfi Illptri 107 Lope PaisePrdie Psle Erdie Illjreqe DiscopaeInvndfe Illptre 112 Register 0x35 Rpop Pointer LSB Bit Type Function Default Ndfpor ExtdRDI10 115 116 Register 0x38 Rpop Path BIP-8 LSB Bit Type Function Default Bit PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0Register 0x39 Rpop Path BIP-8 MSB Register 0x3A Rpop Path Febe LSB Bit Type Function Default Register 0x3B Rpop Path Febe MSB Bit Type Function DefaultBit PFE7 PFE6 PFE5 PFE4 PFE3 PFE2 PFE1 PFE0 Register 0x3C Rpop Auxiliary RDI Bit Type Function Default AprdieAprdiv Aprdie Aprdiv SOS EnssBlkbip Blkbipo 121 Eprdien EprdisrcPersist 123 Ftptr NSEPSE NDF 125 CPTR7 CPTR6CPTR5 CPTR4 CPTR9 CPTR8 APTR7 APTR6APTR5 APTR4 Bit NDF3 NDF2 NDF1 NDF0 APTR9APTR8 130 Register 0x49 Tpop Path Status Bit Type Function Default 132 Register 0x60 Rxcp Configuration Bit Type Function Default DiscorHcsadd Ddscr Register 0x61 Rxcp Configuration Bit Type Function Default CcdisHCSFTR1 HCSFTR0 Hcspass Rxptyp RcainvFiforst Fiforst RCALEVEL0 137 Xferi OVRXfere Fovre 139 Oocdi ChcsiUhcsi Fovri Oocdv LCDC9 LCDC8LCDC7 LCDC6 Bit GFC3 GFC2 GFC1 GFC0 PTI3 PTI2 PTI1 CLP MGFC3 MGFC2MGFC1 MGFC0 CHCS7 CHCS6CHCS5 CHCS4 UHCS7 UHCS6UHCS5 UHCS4 RCELL7 RCELL6RCELL5 RCELL4 148 ICELL7 ICELL6ICELL5 ICELL4 ICELL18 ICELL17ICELL16 Register 0x80 Txcp Configuration Bit Type Function Default TptypDscr Hcsb TCALEVEL0 Register 0x81 Txcp Configuration Bit Type Function Default FIFODP1 FIFODP0 Fifo Depth CellsCell H4INSB 156 Tprtye TsoceTprtyi Tsoci 158 Bit GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 PAYLD7 PAYLD6PAYLD5 PAYLD4 Register 0x87 Txcp Transmit Cell Count 162 Sdlrdi SflrdiLoflrdi Loslrdi 164 Lcdprdi AlrmprdiPaisprdi Lopprdi 166 Lcdeprdi NoalmeprdiNopaiseprdi Pslmeprdi 168 Paisconprdi Nopaisconeprdi Sdins SfinsLofins Losins 171 Paisconpais LopconpaisLoppais Paispais Perdien PrdienPaisen Lopen Alarm Description Bit Z1/S1E SdbereSfbere Coapse Psbfi CoapsiSfberi Sdberi 177 Sfberten SfsmodeSdberten Sdcmode Sfcmode SFSAP7 SFSAP6SFSAP5 SFSAP4 SFSAP23 SFSAP22SFSAP21 SFSAP20 SFSTH7 SFSTH6SFSTH5 SFSTH4 SFDTH7 SFDTH6SFDTH5 SFDTH4 SFCTH7 SFCTH6SFCTH5 SFCTH4 SDSAP7 SDSAP6SDSAP5 SDSAP4 SDSAP23 SDSAP22SDSAP21 SDSAP20 SDSTH7 SDSTH6SDSTH5 SDSTH4 SDDTH7 SDDTH6SDDTH5 SDDTH4 SDCTH7 SDCTH6SDCTH5 SDCTH4 Register 0xF5 Rase Receive K1 Bit Type Function Default Register 0xF6 Rase Receive K2 Bit Type Function Default Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default Test Features Description Test Mode Register Memory Map AddressMaster Test Register Register 0x400 Master Test Bit Type Function Default Test Mode 0 Details Test Mode 0 Read LocationsPmcatst Test Mode 0 Write Locations Jtag Test PortExtest Boundary Scan 000 Instructions Selected Register Instruction Codes IR20 Identification RegisterBoundary Scan Register Boundary Scan Cells Input PadMUX Output Cell Outcell Bidirectional Cell Iocell Output Enable IocellPAD Operation ATM Mapping into the STS-3c STM-1 SPE Transport and Path Overhead Bytes Transport Overhead Bytes Path Overhead Bytes ATM Cell Data Structure PAYLOAD1 PAYLOAD2PAYLOAD3 PAYLOAD4 PAYLOAD5 PAYLOAD6 205 Recommended Berm settings Clocking Options Conceptual Clocking Structure Loopback Operation Line Loopback Mode Serial Diagnostic Loopback Mode Parallel Diagnostic Loopback Mode Control Select Tri-state Enable Jtag SupportTDO TMS Trstb TCK TAP Controller TAP Controller Finite State Machine States Test-Logic-Reset Update-DRRun-Test-Idle Capture-DR Update-IR Shift-IRBoundary Scan Instructions Bypass Idcode StctestBoard Design Recommendations Power Supply Sequencing Power Sequencing Circuit Analog Power Supply Filtering LAN Mode Analog Power Filters with 3.3V Supply Interfacing to ECL or Pecl Devices Interfacing to ECL or Pecl Using the S/UNI-QUAD with a 5 Volt ODL Initializing the S/UNI-QUAD Functional Timing ATM Utopia Level 2 System Interface Multi-PHY Polling and Addressing Receive Cell Interface 225 Absolute Maximum Ratings Absolute Maximum Ratings 16 D.C. Characteristics TBD Input Low Current 100 VIL = GND. Notes 1 Input High Current +10 VIH = VDD. Notes 1Input Low Current +10 VIL = GND. Notes 2 Input High Current +10 VIH = VDD. Notes 2 Microprocessor Interface Timing Characteristics Address to Latch Set-up Time ALE CSB+RDB Intb TSALW ALE CSB+WRB TSALW tHALW TV L TSAW tVWR tHAW 18 A.C. Timing Characteristics Rstb Pulse Width 100 Tfclk Frequency MHz Tfclk Duty CycleTenb Set-up time to Tfclk Tenb Hold time to Tfclk Transmit ATM System Interface Timing Diagram Rfclk Frequency MHz Rfclk Duty CycleRenb Set-up time to Rfclk Renb Hold time to Rfclk Receive ATM System Interface Timing Diagram Tfpi Set-up Time to Tclk High Tfpi Hold Time to Tclk HighTclk High to Tfpo Valid RCLK1-4 High to RFPO1-4 Valid 239 Jtag Port Interface Timing 241 Ordering and Thermal Information Ordering InformationThermal Information Theta Ja Theta Jc 243 Mechanical Information Mechanical Drawing 304 Pin Super Ball Grid Array Sbga 245 Contacting PMC-SIERRA, INC Corporate InformationApplication Information Web Site