PMC-Sierra PM5349 manual Test Features Description, Test Mode Register Memory Map Address

PMC-Sierra, Inc.

S/UNI-QUAD

DATASHEET

PM5349 S/UNI-QUAD

PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)

12 TEST FEATURES DESCRIPTION

Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing.

Test mode registers are used to apply test vectors during production testing of the S/UNI-QUAD. Test mode registers (as opposed to normal mode registers) are selected when TRS (A[10]) is high.

Test mode registers may also be used for board testing. When all of the TSBs within the S/UNI-QUAD are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "Test Mode 0" for details).

In addition, the S/UNI-QUAD also supports a standard IEEE 1149.1 five-signal JTAG boundary scan test port for use in board testing. All digital device inputs may be read and all digital device outputs may be forced via the JTAG test port.

Table 6: Test Mode Register Memory Map

Address	Register
0x000-0x3FF	Normal Mode Registers
0x400	Master Test Register
0x401-0x7FF	Reserved For Test

12.1 Master Test Register

Notes on Test Mode Register Bits:

1.Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read.

2.Writable test mode register bits are not initialized upon reset unless otherwise noted.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 193