PHYADR2, PHYADR1, PHYADR0, Phyen | PMC-Sierra PM5349 guide

PMC-Sierra, Inc.

S/UNI-QUAD

DATASHEET

PM5349 S/UNI-QUAD

PMC-971239	ISSUE 6	SATURN USER NETWORK INTERFACE (155-QUAD)

Register 0x02: S/UNI-QUAD Master System Interface Control

Bit	Type	Function	Default
Bit 7	R/W	PHY_ADR[2]	0
Bit 6	R/W	PHY_ADR[1]	0
Bit 5	R/W	PHY_ADR[0]	0
Bit 4	R/W	PHY_EN	0
Bit 3		Unused	X
Bit 2	R/W	Reserved	0
Bit 1	R/W	Reserved	0
Bit 0	R/W	Reserved	0

PHY_EN:

The PHY_EN enables the System Interface (Utopia bus).

When set to logic zero, all the output signals of the System Interface are held in high impedance. When set to logic one, the System Interface is driven. This register bit must be set to logic one to start using the device. If the System Interface is shared by several PHY layer devices, they should all be configured with their own unique PHY_ADR[2:0] (see below) value before enabling them, otherwise conflicts could occur on the bus resulting in damages to the devices.

PHY_ADR[2:0]:

The PHY_ADR[2:0] is Device Identification Address (PHY_ADR[2:0]). The PHY_ADR[2:0] register bits are the most-significant bits of the address space which this S/UNI-QUAD occupies. When the PHY_ADR[2:0] inputs match the TADR[4:2] or RADR[4:2] inputs, then one of the four quadrants (as determined by the TADR[1:0] or RADR[1:0] inputs) in this S/UNI-QUAD is selected for transmit or receive operations. Note that the null-PHY address 0x1F is the null-PHY address and cannot be assigned to any port on the S/UNI-QUAD.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

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PMC-Sierra PM5349 manual PHYADR2, PHYADR1, PHYADR0, Phyen, Bit Unused Reserved

Contents

UNI-QUAD Saturn User Network Interface Revision History Issue Issue Date Details of Change Contents Receive Line Overhead Processor Rlop Transmit ATM Cell Processor Txcp Analog Power Supply Filtering Features GeneralSonet Receiver Sonet Transmitter Receive ATM Processor Transmit ATM Processor Applications References Definitions Application Examples Typical STS-3c STM-1 ATM Switch Port Application CS B Block Diagram Description PM5349 S/UNI-QUAD Bottom View PIN Diagram PIN Description Line Side Interface Signals Pin Name Type Function Pin Name Type Function Tclk Tfpi TDAT9 TfpoTDAT8 TDAT7 Tsoc Tprty TADR4 TenbTADR3 TADR2 Tfclk TCA DTCA3 DTCA4DTCA2 DTCA1 Rprty RsocRenb RADR3 RADR4RADR2 RADR1 DRCA3 DRCA4DRCA2 DRCA1 CSB Microprocessor Interface Signals Pin Name Type FunctionRDB WRB Rstb ALEIntb Jtag Test Access Port TAP Signals Pin Name Type Function Power and Ground Pin Name Type Function Analog Signals Pin Name Type Function AA3 VDDAB2 AC1 AA2 VSSAB1 AB3 AC2 AC6 AC8 AA6 QAVD1 QavdQAVD2 Qavs AC3 AVSTAVS1A CSU TAVS1B CSU TRSTB, TCK, TMS, TDI, TDO 5V tolerant I/O’s Clock Recovery Functional DescriptionReceive Line Interface Crsi Serial to Parallel Converter Receive Section Overhead Processor RsopFramer Error Monitor Loss of SignalDescramble Loss of Frame Error Monitor BlockReceive Line Overhead Processor Rlop Line RDI Detect PM5349 S/UNI-QUAD Synchronization Status Extraction Bit Error Rate Monitor Pointer Interpreter Receive Path Overhead Processor Rpop Pointer Interpreter Event Indications Description LOP AIS PM5349 S/UNI-QUAD Pointer Interpreter Transition Description SPE Timing Cell Delineation Receive ATM Cell Processor Rxcp Cell Filter and HCS Verification Descrambler HCS Verification State Diagram Performance Monitor Transmit Line Interface CspiClock Synthesis Transmit Section Overhead Processor Tsop Parallel to Serial ConverterLine AIS Insert BIP-8 Insert Scrambler Framing and Identity InsertTransmit Line Overhead Processor Tlop APS Insert Line Febe Insert Transmit Path Overhead Processor TpopPointer Generator Febe Calculate BIP-8 CalculateTransmit ATM Cell Processor Txcp Idle/Unassigned Cell Generator Utopia Level 2 System Interface HCS GeneratorReceive ATM Interface Transmit ATM Interface Jtag Test Access Port Microprocessor InterfaceRegister Memory Map REG Address A100 Description Rxcp Configuration Tpop Path Signal Label362 Rxcp FIFO/UTOPIA Control & Config 363 Rxcp Interrupt Enables and Counter Status Txcp Transmit Cell Status/Configuration Options Txcp ConfigurationTxcp Interrupt Enable/Status Rxcp Idle Cell Count LSB 06F 16F 26F 36F Rase APS K1 0EF 1EF 2EF 3EFRase APS K2 0FB 1FB 2FB 3FB 0FE 1FE 2FE 3FE UNI-QUAD Master Test RegisterReserved for Test Normal Mode Register Description TYPE3 ResetTYPE2 TYPE1 TFPOCH1 Bit ReservedTFPOCH0 Tfpo Channel Selection PM5349 S/UNI-QUAD PHYADR1 PHYADR2PHYADR0 Phyen Rfclka TclkaTfclka Refclka RCLK2A RCLK1ARCLK3A RCLK4A CHNL4I CsuiCHNL3I CHNL2I Csui TIP Chreset Autolfebe AutopfebeAutolrdi Autoprdi Rxdinv TfpienLoopt Sdle Rxdinv PM5349 S/UNI-QUAD Crui RaseiTxcpi Rxcpi Txcpi Trooli TroolvTroole PM5349 S/UNI-QUAD Rdooli RrooliRroolv Rdoolv Rdooli PM5349 S/UNI-QUAD Foof BipwordALGO2 Bipee DDS Losi BipeiLofi Oofi Bipei Bit Type Function Default Bit SBE7 SBE6 SBE5 SBE4 SBE3 SBE2 SBE1 SBE0Register 0x13 Rsop Section BIP-8 MSB Lais Register 0x14 Tsop Control Bit Type Function Default Dlos Register 0x15 Tsop Diagnostic Bit Type Function DefaultDBIP8 DFP Register 0x18 Rlop Control/Status Bit Type Function Default Lrdidet Lrdie LaiseFebei Laisi Febee Bit LBE7 LBE6 LBE5 LBE4 LBE3 LBE2 LBE1 LBE0 Register 0x1B Rlop Line BIP-24Bit LBE15 LBE14 LBE13 LBE12 LBE11 LBE10 LBE9 LBE8 Register 0x1C Rlop Line BIP-24 MSB Bit Type Function Default Bit LFE7 LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Register 0x1D Rlop Line Febe LSB Bit Type Function DefaultRegister 0x1E Rlop Line Febe Bit LFE15 LFE14 LFE13 LFE12 LFE11 LFE10 LFE9 LFE8 Register 0x1F Rlop Line Febe MSB Bit Type Function Default Register 0x20 Tlop Control Bit Type Function Default ApsregLrdi Dbip Register 0x21 Tlop Diagnostic Bit Type Function Default Register 0x22 Tlop Transmit K1 Bit Type Function Default Register 0x23 Tlop Transmit K2 Bit Type Function Default PM5349 S/UNI-QUAD Lopv LopconvPaisonv Paisv Plopv Paisconv ERDIV2 IinvcntERDIV1 ERDIV0 Lopi PsliPaisi Prdii 104 Erdii Discopai IlljreqiInvndfi Illptri 107 Lope PaisePrdie Psle Erdie Discopae IlljreqeInvndfe Illptre 112 Register 0x35 Rpop Pointer LSB Bit Type Function Default Ndfpor ExtdRDI10 115 116 Register 0x38 Rpop Path BIP-8 LSB Bit Type Function Default Bit PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0Register 0x39 Rpop Path BIP-8 MSB Register 0x3A Rpop Path Febe LSB Bit Type Function Default Register 0x3B Rpop Path Febe MSB Bit Type Function DefaultBit PFE7 PFE6 PFE5 PFE4 PFE3 PFE2 PFE1 PFE0 Aprdie Register 0x3C Rpop Auxiliary RDI Bit Type Function DefaultAprdiv Aprdie Aprdiv Enss SOSBlkbip Blkbipo 121 Eprdien EprdisrcPersist 123 NSE FtptrPSE NDF 125 CPTR6 CPTR7CPTR5 CPTR4 CPTR8 CPTR9 APTR6 APTR7APTR5 APTR4 Bit NDF3 NDF2 NDF1 NDF0 APTR9APTR8 130 Register 0x49 Tpop Path Status Bit Type Function Default 132 Discor Register 0x60 Rxcp Configuration Bit Type Function DefaultHcsadd Ddscr Ccdis Register 0x61 Rxcp Configuration Bit Type Function DefaultHCSFTR1 HCSFTR0 Hcspass Rcainv RxptypFiforst Fiforst RCALEVEL0 137 OVR XferiXfere Fovre 139 Chcsi OocdiUhcsi Fovri Oocdv LCDC8 LCDC9LCDC7 LCDC6 CLP Bit GFC3 GFC2 GFC1 GFC0 PTI3 PTI2 PTI1 MGFC2 MGFC3MGFC1 MGFC0 CHCS6 CHCS7CHCS5 CHCS4 UHCS6 UHCS7UHCS5 UHCS4 RCELL6 RCELL7RCELL5 RCELL4 148 ICELL6 ICELL7ICELL5 ICELL4 ICELL18 ICELL17ICELL16 Tptyp Register 0x80 Txcp Configuration Bit Type Function DefaultDscr Hcsb TCALEVEL0 Register 0x81 Txcp Configuration Bit Type Function Default FIFODP1 FIFODP0 Fifo Depth CellsCell H4INSB 156 Tsoce TprtyeTprtyi Tsoci 158 Bit GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 PAYLD6 PAYLD7PAYLD5 PAYLD4 Register 0x87 Txcp Transmit Cell Count 162 Sflrdi SdlrdiLoflrdi Loslrdi 164 Alrmprdi LcdprdiPaisprdi Lopprdi 166 Noalmeprdi LcdeprdiNopaiseprdi Pslmeprdi 168 Nopaisconeprdi Paisconprdi Sfins SdinsLofins Losins 171 Lopconpais PaisconpaisLoppais Paispais Prdien PerdienPaisen Lopen Alarm Description Sdbere Bit Z1/S1ESfbere Coapse Coapsi PsbfiSfberi Sdberi 177 Sfsmode SfbertenSdberten Sdcmode Sfcmode SFSAP6 SFSAP7SFSAP5 SFSAP4 SFSAP22 SFSAP23SFSAP21 SFSAP20 SFSTH6 SFSTH7SFSTH5 SFSTH4 SFDTH6 SFDTH7SFDTH5 SFDTH4 SFCTH6 SFCTH7SFCTH5 SFCTH4 SDSAP6 SDSAP7SDSAP5 SDSAP4 SDSAP22 SDSAP23SDSAP21 SDSAP20 SDSTH6 SDSTH7SDSTH5 SDSTH4 SDDTH6 SDDTH7SDDTH5 SDDTH4 SDCTH6 SDCTH7SDCTH5 SDCTH4 Register 0xF5 Rase Receive K1 Bit Type Function Default Register 0xF6 Rase Receive K2 Bit Type Function Default Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default Test Features Description Test Mode Register Memory Map AddressMaster Test Register Register 0x400 Master Test Bit Type Function Default Test Mode 0 Details Test Mode 0 Read LocationsPmcatst Jtag Test Port Test Mode 0 Write LocationsExtest Boundary Scan 000 Instructions Selected Register Instruction Codes IR20 Identification RegisterBoundary Scan Register Boundary Scan Cells Input PadMUX Bidirectional Cell Iocell Output Cell Outcell Output Enable IocellPAD ATM Mapping into the STS-3c STM-1 SPE Operation Transport Overhead Bytes Transport and Path Overhead Bytes Path Overhead Bytes PAYLOAD1 PAYLOAD2 ATM Cell Data StructurePAYLOAD3 PAYLOAD4 PAYLOAD5 PAYLOAD6 205 Clocking Options Recommended Berm settings Conceptual Clocking Structure Loopback Operation Line Loopback Mode Serial Diagnostic Loopback Mode Parallel Diagnostic Loopback Mode Jtag Support Control Select Tri-state EnableTDO TMS Trstb TCK TAP Controller TAP Controller Finite State Machine Update-DR States Test-Logic-ResetRun-Test-Idle Capture-DR Shift-IR Update-IRBoundary Scan Instructions Bypass Idcode StctestBoard Design Recommendations Power Supply Sequencing Analog Power Supply Filtering Power Sequencing Circuit Interfacing to ECL or Pecl Devices LAN Mode Analog Power Filters with 3.3V Supply Interfacing to ECL or Pecl Initializing the S/UNI-QUAD Using the S/UNI-QUAD with a 5 Volt ODL ATM Utopia Level 2 System Interface Functional Timing Multi-PHY Polling and Addressing Receive Cell Interface 225 Absolute Maximum Ratings Absolute Maximum Ratings TBD 16 D.C. Characteristics Input High Current +10 VIH = VDD. Notes 1 Input Low Current 100 VIL = GND. Notes 1Input Low Current +10 VIL = GND. Notes 2 Input High Current +10 VIH = VDD. Notes 2 Address to Latch Set-up Time Microprocessor Interface Timing Characteristics ALE CSB+RDB Intb TSALW TSALW tHALW TV L TSAW tVWR tHAW ALE CSB+WRB Rstb Pulse Width 100 18 A.C. Timing Characteristics Tfclk Duty Cycle Tfclk Frequency MHzTenb Set-up time to Tfclk Tenb Hold time to Tfclk Transmit ATM System Interface Timing Diagram Rfclk Duty Cycle Rfclk Frequency MHzRenb Set-up time to Rfclk Renb Hold time to Rfclk Receive ATM System Interface Timing Diagram Tfpi Hold Time to Tclk High Tfpi Set-up Time to Tclk HighTclk High to Tfpo Valid RCLK1-4 High to RFPO1-4 Valid 239 Jtag Port Interface Timing 241 Ordering Information Ordering and Thermal InformationThermal Information Theta Ja Theta Jc 243 Mechanical Drawing 304 Pin Super Ball Grid Array Sbga Mechanical Information 245 Corporate Information Contacting PMC-SIERRA, INCApplication Information Web Site