Lrdidet | PMC-Sierra PM5349 guide

PMC-Sierra, Inc.

S/UNI-QUAD

DATASHEET

PM5349 S/UNI-QUAD

PMC-971239	ISSUE 6	SATURN USER NETWORK INTERFACE (155-QUAD)

LRDIDET:

The LRDIDET bit determines the Line LRDI detection algorithm. When LRDIDET is set to logic one, Line LRDI is declared when a 110 binary pattern is detected in bits 6,7 and 8 of the K2 byte for three consecutive frames. When LRDIDET is set to logic zero, Line LRDI is declared when a 110 binary pattern is detected in bits 6,7 and 8 of the K2 byte for five consecutive frames.

AISDET:

The AISDET bit determines the Line AIS detection algorithm. When AISDET is set to logic one, Line AIS is declared when a 111 binary pattern is detected in bits 6,7 and 8 of the K2 byte for three consecutive frames. When AISDET is set to logic zero, Line AIS is declared when a 111 binary pattern is detected in bits 6,7 and 8 of the K2 byte for five consecutive frames.

ALLONES:

The ALLONES bit controls automatically forcing the SONET frame passed to downstream blocks to logical all-ones whenever LAIS is detected. When ALLONES is set to logic one, the SONET frame is forced to logic one immediately when the LAIS alarm is declared. When LAIS is removed, the received byte is immediately returned to carrying data. When ALLONES is set to logic zero, the received byte carries the data regardless of the state of LAIS.

BIPWORD:

The BIPWORD bit controls the accumulation of B2 errors. When BIPWORD is logic one, the B2 error event counter is incremented only once per frame whenever one or more B2 bit errors occur during that frame. When BIPWORD is logic zero, the B2 error event counter is incremented for each B2 bit error that occurs during that frame (the counter can be incremented up to 24 times per frame).

Reserved:

The reserved bits must be programmed to logic zero for proper operation.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

88

Image 94

PMC-Sierra PM5349 manual Lrdidet

Contents

UNI-QUAD Saturn User Network Interface Issue Issue Date Details of Change Revision History Contents Receive Line Overhead Processor Rlop Transmit ATM Cell Processor Txcp Analog Power Supply Filtering General FeaturesSonet Receiver Receive ATM Processor Sonet Transmitter Transmit ATM Processor Applications References Definitions Typical STS-3c STM-1 ATM Switch Port Application Application Examples Block Diagram CS B Description PM5349 S/UNI-QUAD PIN Diagram Bottom View Line Side Interface Signals Pin Name Type Function PIN Description Pin Name Type Function Tfpi Tclk TDAT8 TfpoTDAT9 TDAT7 Tprty Tsoc TADR3 TenbTADR4 TADR2 TCA Tfclk DTCA2 DTCA4DTCA3 DTCA1 Rsoc RprtyRenb RADR2 RADR4RADR3 RADR1 DRCA2 DRCA4DRCA3 DRCA1 RDB Microprocessor Interface Signals Pin Name Type FunctionCSB WRB ALE RstbIntb Jtag Test Access Port TAP Signals Pin Name Type Function Analog Signals Pin Name Type Function Power and Ground Pin Name Type Function AB2 VDDAA3 AC1 AB1 AB3 VSSAA2 AC2 AC6 AC8 QAVD2 QavdAA6 QAVD1 Qavs TAVS1A CSU AVSAC3 TAVS1B CSU 5V tolerant I/O’s TRSTB, TCK, TMS, TDI, TDO Functional Description Clock RecoveryReceive Line Interface Crsi Receive Section Overhead Processor Rsop Serial to Parallel ConverterFramer Loss of Signal Error MonitorDescramble Receive Line Overhead Processor Rlop Error Monitor BlockLoss of Frame Line RDI Detect PM5349 S/UNI-QUAD Bit Error Rate Monitor Synchronization Status Extraction Receive Path Overhead Processor Rpop Pointer Interpreter LOP AIS Pointer Interpreter Event Indications Description PM5349 S/UNI-QUAD Pointer Interpreter Transition Description SPE Timing Receive ATM Cell Processor Rxcp Cell Delineation Descrambler Cell Filter and HCS Verification HCS Verification State Diagram Transmit Line Interface Cspi Performance MonitorClock Synthesis Line AIS Insert Parallel to Serial ConverterTransmit Section Overhead Processor Tsop BIP-8 Insert Transmit Line Overhead Processor Tlop Framing and Identity InsertScrambler APS Insert Transmit Path Overhead Processor Tpop Line Febe InsertPointer Generator Transmit ATM Cell Processor Txcp BIP-8 CalculateFebe Calculate Idle/Unassigned Cell Generator Receive ATM Interface HCS GeneratorUtopia Level 2 System Interface Transmit ATM Interface Microprocessor Interface Jtag Test Access PortRegister Memory Map REG Address A100 Description 362 Rxcp FIFO/UTOPIA Control & Config Tpop Path Signal LabelRxcp Configuration 363 Rxcp Interrupt Enables and Counter Status Txcp Interrupt Enable/Status Txcp ConfigurationTxcp Transmit Cell Status/Configuration Options Rxcp Idle Cell Count LSB 06F 16F 26F 36F Rase APS K2 0EF 1EF 2EF 3EFRase APS K1 0FB 1FB 2FB 3FB UNI-QUAD Master Test Register 0FE 1FE 2FE 3FEReserved for Test Normal Mode Register Description TYPE2 ResetTYPE3 TYPE1 TFPOCH0 Bit ReservedTFPOCH1 Tfpo Channel Selection PM5349 S/UNI-QUAD PHYADR0 PHYADR2PHYADR1 Phyen Tfclka TclkaRfclka Refclka RCLK3A RCLK1ARCLK2A RCLK4A CHNL3I CsuiCHNL4I CHNL2I Csui Chreset TIP Autolrdi AutopfebeAutolfebe Autoprdi Loopt TfpienRxdinv Sdle Rxdinv PM5349 S/UNI-QUAD Txcpi RaseiCrui Rxcpi Txcpi Troolv TrooliTroole PM5349 S/UNI-QUAD Rroolv RrooliRdooli Rdoolv Rdooli PM5349 S/UNI-QUAD ALGO2 BipwordFoof Bipee DDS Lofi BipeiLosi Oofi Bipei Bit SBE7 SBE6 SBE5 SBE4 SBE3 SBE2 SBE1 SBE0 Bit Type Function DefaultRegister 0x13 Rsop Section BIP-8 MSB Register 0x14 Tsop Control Bit Type Function Default Lais DBIP8 Register 0x15 Tsop Diagnostic Bit Type Function DefaultDlos DFP Register 0x18 Rlop Control/Status Bit Type Function Default Lrdidet Febei LaiseLrdie Laisi Febee Register 0x1B Rlop Line BIP-24 Bit LBE7 LBE6 LBE5 LBE4 LBE3 LBE2 LBE1 LBE0Bit LBE15 LBE14 LBE13 LBE12 LBE11 LBE10 LBE9 LBE8 Register 0x1C Rlop Line BIP-24 MSB Bit Type Function Default Register 0x1E Rlop Line Febe Register 0x1D Rlop Line Febe LSB Bit Type Function DefaultBit LFE7 LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Bit LFE15 LFE14 LFE13 LFE12 LFE11 LFE10 LFE9 LFE8 Register 0x1F Rlop Line Febe MSB Bit Type Function Default Apsreg Register 0x20 Tlop Control Bit Type Function DefaultLrdi Register 0x21 Tlop Diagnostic Bit Type Function Default Dbip Register 0x22 Tlop Transmit K1 Bit Type Function Default Register 0x23 Tlop Transmit K2 Bit Type Function Default PM5349 S/UNI-QUAD Paisonv LopconvLopv Paisv Paisconv Plopv ERDIV1 IinvcntERDIV2 ERDIV0 Paisi PsliLopi Prdii 104 Erdii Invndfi IlljreqiDiscopai Illptri 107 Paise LopePrdie Psle Erdie Invndfe IlljreqeDiscopae Illptre 112 Register 0x35 Rpop Pointer LSB Bit Type Function Default Extd NdfporRDI10 115 116 Bit PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0 Register 0x38 Rpop Path BIP-8 LSB Bit Type Function DefaultRegister 0x39 Rpop Path BIP-8 MSB Register 0x3B Rpop Path Febe MSB Bit Type Function Default Register 0x3A Rpop Path Febe LSB Bit Type Function DefaultBit PFE7 PFE6 PFE5 PFE4 PFE3 PFE2 PFE1 PFE0 Aprdiv Aprdie Register 0x3C Rpop Auxiliary RDI Bit Type Function DefaultAprdie Aprdiv Blkbip SOSEnss Blkbipo 121 Eprdisrc EprdienPersist 123 PSE FtptrNSE NDF 125 CPTR5 CPTR7CPTR6 CPTR4 CPTR9 CPTR8 APTR5 APTR7APTR6 APTR4 APTR9 Bit NDF3 NDF2 NDF1 NDF0APTR8 130 Register 0x49 Tpop Path Status Bit Type Function Default 132 Hcsadd Register 0x60 Rxcp Configuration Bit Type Function DefaultDiscor Ddscr HCSFTR1 Register 0x61 Rxcp Configuration Bit Type Function DefaultCcdis HCSFTR0 Hcspass Fiforst RxptypRcainv Fiforst RCALEVEL0 137 Xfere XferiOVR Fovre 139 Uhcsi OocdiChcsi Fovri Oocdv LCDC7 LCDC9LCDC8 LCDC6 Bit GFC3 GFC2 GFC1 GFC0 PTI3 PTI2 PTI1 CLP MGFC1 MGFC3MGFC2 MGFC0 CHCS5 CHCS7CHCS6 CHCS4 UHCS5 UHCS7UHCS6 UHCS4 RCELL5 RCELL7RCELL6 RCELL4 148 ICELL5 ICELL7ICELL6 ICELL4 ICELL17 ICELL18ICELL16 Dscr Register 0x80 Txcp Configuration Bit Type Function DefaultTptyp Hcsb TCALEVEL0 Register 0x81 Txcp Configuration Bit Type Function Default Cells FIFODP1 FIFODP0 Fifo DepthCell H4INSB 156 Tprtyi TprtyeTsoce Tsoci 158 Bit GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 PAYLD5 PAYLD7PAYLD6 PAYLD4 Register 0x87 Txcp Transmit Cell Count 162 Loflrdi SdlrdiSflrdi Loslrdi 164 Paisprdi LcdprdiAlrmprdi Lopprdi 166 Nopaiseprdi LcdeprdiNoalmeprdi Pslmeprdi 168 Paisconprdi Nopaisconeprdi Lofins SdinsSfins Losins 171 Loppais PaisconpaisLopconpais Paispais Paisen PerdienPrdien Lopen Alarm Description Sfbere Bit Z1/S1ESdbere Coapse Sfberi PsbfiCoapsi Sdberi 177 Sdberten SfbertenSfsmode Sdcmode Sfcmode SFSAP5 SFSAP7SFSAP6 SFSAP4 SFSAP21 SFSAP23SFSAP22 SFSAP20 SFSTH5 SFSTH7SFSTH6 SFSTH4 SFDTH5 SFDTH7SFDTH6 SFDTH4 SFCTH5 SFCTH7SFCTH6 SFCTH4 SDSAP5 SDSAP7SDSAP6 SDSAP4 SDSAP21 SDSAP23SDSAP22 SDSAP20 SDSTH5 SDSTH7SDSTH6 SDSTH4 SDDTH5 SDDTH7SDDTH6 SDDTH4 SDCTH5 SDCTH7SDCTH6 SDCTH4 Register 0xF5 Rase Receive K1 Bit Type Function Default Register 0xF6 Rase Receive K2 Bit Type Function Default Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default Test Mode Register Memory Map Address Test Features DescriptionMaster Test Register Register 0x400 Master Test Bit Type Function Default Test Mode 0 Read Locations Test Mode 0 DetailsPmcatst Extest Test Mode 0 Write LocationsJtag Test Port Boundary Scan 000 Identification Register Instructions Selected Register Instruction Codes IR20Boundary Scan Register Input Pad Boundary Scan CellsMUX Output Cell Outcell Bidirectional Cell Iocell Iocell Output EnablePAD Operation ATM Mapping into the STS-3c STM-1 SPE Transport and Path Overhead Bytes Transport Overhead Bytes Path Overhead Bytes PAYLOAD3 PAYLOAD4 ATM Cell Data StructurePAYLOAD1 PAYLOAD2 PAYLOAD5 PAYLOAD6 205 Recommended Berm settings Clocking Options Conceptual Clocking Structure Loopback Operation Line Loopback Mode Serial Diagnostic Loopback Mode Parallel Diagnostic Loopback Mode TDO TMS Control Select Tri-state EnableJtag Support Trstb TCK TAP Controller TAP Controller Finite State Machine Run-Test-Idle States Test-Logic-ResetUpdate-DR Capture-DR Boundary Scan Instructions Update-IRShift-IR Bypass Stctest IdcodeBoard Design Recommendations Power Supply Sequencing Power Sequencing Circuit Analog Power Supply Filtering LAN Mode Analog Power Filters with 3.3V Supply Interfacing to ECL or Pecl Devices Interfacing to ECL or Pecl Using the S/UNI-QUAD with a 5 Volt ODL Initializing the S/UNI-QUAD Functional Timing ATM Utopia Level 2 System Interface Multi-PHY Polling and Addressing Receive Cell Interface 225 Absolute Maximum Ratings Absolute Maximum Ratings 16 D.C. Characteristics TBD Input Low Current +10 VIL = GND. Notes 2 Input Low Current 100 VIL = GND. Notes 1Input High Current +10 VIH = VDD. Notes 1 Input High Current +10 VIH = VDD. Notes 2 Microprocessor Interface Timing Characteristics Address to Latch Set-up Time ALE CSB+RDB Intb TSALW ALE CSB+WRB TSALW tHALW TV L TSAW tVWR tHAW 18 A.C. Timing Characteristics Rstb Pulse Width 100 Tenb Set-up time to Tfclk Tfclk Frequency MHzTfclk Duty Cycle Tenb Hold time to Tfclk Transmit ATM System Interface Timing Diagram Renb Set-up time to Rfclk Rfclk Frequency MHzRfclk Duty Cycle Renb Hold time to Rfclk Receive ATM System Interface Timing Diagram Tclk High to Tfpo Valid Tfpi Set-up Time to Tclk HighTfpi Hold Time to Tclk High RCLK1-4 High to RFPO1-4 Valid 239 Jtag Port Interface Timing 241 Thermal Information Ordering and Thermal InformationOrdering Information Theta Ja Theta Jc 243 Mechanical Information Mechanical Drawing 304 Pin Super Ball Grid Array Sbga 245 Application Information Contacting PMC-SIERRA, INCCorporate Information Web Site