TAP Controller | PMC-Sierra PM5349 guide

PMC-Sierra, Inc.

S/UNI-QUAD

DATASHEET

PM5349 S/UNI-QUAD

PMC-971239	ISSUE 6	SATURN USER NETWORK INTERFACE (155-QUAD)

The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a single- bit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code.

The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs.

13.6.1TAP Controller

The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

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PMC-Sierra PM5349 manual TAP Controller

Contents

UNI-QUAD Saturn User Network Interface Revision History Issue Issue Date Details of Change Contents Receive Line Overhead Processor Rlop Transmit ATM Cell Processor Txcp Analog Power Supply Filtering Features GeneralSonet Receiver Sonet Transmitter Receive ATM Processor Transmit ATM Processor Applications References Definitions Application Examples Typical STS-3c STM-1 ATM Switch Port Application CS B Block Diagram Description PM5349 S/UNI-QUAD Bottom View PIN Diagram PIN Description Line Side Interface Signals Pin Name Type Function Pin Name Type Function Tclk Tfpi TDAT7 TfpoTDAT9 TDAT8 Tsoc Tprty TADR2 TenbTADR4 TADR3 Tfclk TCA DTCA1 DTCA4DTCA3 DTCA2 Rprty RsocRenb RADR1 RADR4RADR3 RADR2 DRCA1 DRCA4DRCA3 DRCA2 WRB Microprocessor Interface Signals Pin Name Type FunctionCSB RDB Rstb ALEIntb Jtag Test Access Port TAP Signals Pin Name Type Function Power and Ground Pin Name Type Function Analog Signals Pin Name Type Function AC1 VDDAA3 AB2 AC2 AC6 AC8 VSSAA2 AB1 AB3 Qavs QavdAA6 QAVD1 QAVD2 TAVS1B CSU AVSAC3 TAVS1A CSU TRSTB, TCK, TMS, TDI, TDO 5V tolerant I/O’s Clock Recovery Functional DescriptionReceive Line Interface Crsi Serial to Parallel Converter Receive Section Overhead Processor RsopFramer Error Monitor Loss of SignalDescramble Line RDI Detect Error Monitor BlockLoss of Frame Receive Line Overhead Processor Rlop PM5349 S/UNI-QUAD Synchronization Status Extraction Bit Error Rate Monitor Pointer Interpreter Receive Path Overhead Processor Rpop Pointer Interpreter Event Indications Description LOP AIS PM5349 S/UNI-QUAD Pointer Interpreter Transition Description SPE Timing Cell Delineation Receive ATM Cell Processor Rxcp Cell Filter and HCS Verification Descrambler HCS Verification State Diagram Performance Monitor Transmit Line Interface CspiClock Synthesis BIP-8 Insert Parallel to Serial ConverterTransmit Section Overhead Processor Tsop Line AIS Insert APS Insert Framing and Identity InsertScrambler Transmit Line Overhead Processor Tlop Line Febe Insert Transmit Path Overhead Processor TpopPointer Generator Idle/Unassigned Cell Generator BIP-8 CalculateFebe Calculate Transmit ATM Cell Processor Txcp Transmit ATM Interface HCS GeneratorUtopia Level 2 System Interface Receive ATM Interface Jtag Test Access Port Microprocessor InterfaceRegister Memory Map REG Address A100 Description 363 Rxcp Interrupt Enables and Counter Status Tpop Path Signal LabelRxcp Configuration 362 Rxcp FIFO/UTOPIA Control & Config Rxcp Idle Cell Count LSB 06F 16F 26F 36F Txcp ConfigurationTxcp Transmit Cell Status/Configuration Options Txcp Interrupt Enable/Status 0FB 1FB 2FB 3FB 0EF 1EF 2EF 3EFRase APS K1 Rase APS K2 0FE 1FE 2FE 3FE UNI-QUAD Master Test RegisterReserved for Test Normal Mode Register Description TYPE1 ResetTYPE3 TYPE2 Tfpo Channel Selection Bit ReservedTFPOCH1 TFPOCH0 PM5349 S/UNI-QUAD Phyen PHYADR2PHYADR1 PHYADR0 Refclka TclkaRfclka Tfclka RCLK4A RCLK1ARCLK2A RCLK3A CHNL2I CsuiCHNL4I CHNL3I Csui TIP Chreset Autoprdi AutopfebeAutolfebe Autolrdi Sdle TfpienRxdinv Loopt Rxdinv PM5349 S/UNI-QUAD Rxcpi RaseiCrui Txcpi Txcpi Trooli TroolvTroole PM5349 S/UNI-QUAD Rdoolv RrooliRdooli Rroolv Rdooli PM5349 S/UNI-QUAD Bipee BipwordFoof ALGO2 DDS Oofi BipeiLosi Lofi Bipei Bit Type Function Default Bit SBE7 SBE6 SBE5 SBE4 SBE3 SBE2 SBE1 SBE0Register 0x13 Rsop Section BIP-8 MSB Lais Register 0x14 Tsop Control Bit Type Function Default DFP Register 0x15 Tsop Diagnostic Bit Type Function DefaultDlos DBIP8 Register 0x18 Rlop Control/Status Bit Type Function Default Lrdidet Laisi LaiseLrdie Febei Febee Bit LBE7 LBE6 LBE5 LBE4 LBE3 LBE2 LBE1 LBE0 Register 0x1B Rlop Line BIP-24Bit LBE15 LBE14 LBE13 LBE12 LBE11 LBE10 LBE9 LBE8 Register 0x1C Rlop Line BIP-24 MSB Bit Type Function Default Bit LFE15 LFE14 LFE13 LFE12 LFE11 LFE10 LFE9 LFE8 Register 0x1D Rlop Line Febe LSB Bit Type Function DefaultBit LFE7 LFE6 LFE5 LFE4 LFE3 LFE2 LFE1 LFE0 Register 0x1E Rlop Line Febe Register 0x1F Rlop Line Febe MSB Bit Type Function Default Register 0x20 Tlop Control Bit Type Function Default ApsregLrdi Dbip Register 0x21 Tlop Diagnostic Bit Type Function Default Register 0x22 Tlop Transmit K1 Bit Type Function Default Register 0x23 Tlop Transmit K2 Bit Type Function Default PM5349 S/UNI-QUAD Paisv LopconvLopv Paisonv Plopv Paisconv ERDIV0 IinvcntERDIV2 ERDIV1 Prdii PsliLopi Paisi 104 Erdii Illptri IlljreqiDiscopai Invndfi 107 Lope PaisePrdie Psle Erdie Illptre IlljreqeDiscopae Invndfe 112 Register 0x35 Rpop Pointer LSB Bit Type Function Default Ndfpor ExtdRDI10 115 116 Register 0x38 Rpop Path BIP-8 LSB Bit Type Function Default Bit PBE7 PBE6 PBE5 PBE4 PBE3 PBE2 PBE1 PBE0Register 0x39 Rpop Path BIP-8 MSB Register 0x3A Rpop Path Febe LSB Bit Type Function Default Register 0x3B Rpop Path Febe MSB Bit Type Function DefaultBit PFE7 PFE6 PFE5 PFE4 PFE3 PFE2 PFE1 PFE0 Aprdiv Register 0x3C Rpop Auxiliary RDI Bit Type Function DefaultAprdie Aprdiv Aprdie Blkbipo SOSEnss Blkbip 121 Eprdien EprdisrcPersist 123 NDF FtptrNSE PSE 125 CPTR4 CPTR7CPTR6 CPTR5 CPTR8 CPTR9 APTR4 APTR7APTR6 APTR5 Bit NDF3 NDF2 NDF1 NDF0 APTR9APTR8 130 Register 0x49 Tpop Path Status Bit Type Function Default 132 Ddscr Register 0x60 Rxcp Configuration Bit Type Function DefaultDiscor Hcsadd HCSFTR0 Register 0x61 Rxcp Configuration Bit Type Function DefaultCcdis HCSFTR1 Hcspass Fiforst RCALEVEL0 RxptypRcainv Fiforst 137 Fovre XferiOVR Xfere 139 Fovri OocdiChcsi Uhcsi Oocdv LCDC6 LCDC9LCDC8 LCDC7 CLP Bit GFC3 GFC2 GFC1 GFC0 PTI3 PTI2 PTI1 MGFC0 MGFC3MGFC2 MGFC1 CHCS4 CHCS7CHCS6 CHCS5 UHCS4 UHCS7UHCS6 UHCS5 RCELL4 RCELL7RCELL6 RCELL5 148 ICELL4 ICELL7ICELL6 ICELL5 ICELL18 ICELL17ICELL16 Hcsb Register 0x80 Txcp Configuration Bit Type Function DefaultTptyp Dscr TCALEVEL0 Register 0x81 Txcp Configuration Bit Type Function Default FIFODP1 FIFODP0 Fifo Depth CellsCell H4INSB 156 Tsoci TprtyeTsoce Tprtyi 158 Bit GFC3 GFC2 GFC1 GFC0 PTI2 PTI1 PTI0 PAYLD4 PAYLD7PAYLD6 PAYLD5 Register 0x87 Txcp Transmit Cell Count 162 Loslrdi SdlrdiSflrdi Loflrdi 164 Lopprdi LcdprdiAlrmprdi Paisprdi 166 Pslmeprdi LcdeprdiNoalmeprdi Nopaiseprdi 168 Nopaisconeprdi Paisconprdi Losins SdinsSfins Lofins 171 Paispais PaisconpaisLopconpais Loppais Lopen PerdienPrdien Paisen Alarm Description Coapse Bit Z1/S1ESdbere Sfbere Sdberi PsbfiCoapsi Sfberi 177 Sdcmode SfbertenSfsmode Sdberten Sfcmode SFSAP4 SFSAP7SFSAP6 SFSAP5 SFSAP20 SFSAP23SFSAP22 SFSAP21 SFSTH4 SFSTH7SFSTH6 SFSTH5 SFDTH4 SFDTH7SFDTH6 SFDTH5 SFCTH4 SFCTH7SFCTH6 SFCTH5 SDSAP4 SDSAP7SDSAP6 SDSAP5 SDSAP20 SDSAP23SDSAP22 SDSAP21 SDSTH4 SDSTH7SDSTH6 SDSTH5 SDDTH4 SDDTH7SDDTH6 SDDTH5 SDCTH4 SDCTH7SDCTH6 SDCTH5 Register 0xF5 Rase Receive K1 Bit Type Function Default Register 0xF6 Rase Receive K2 Bit Type Function Default Register 0xF7 Rase Receive Z1/S1 Bit Type Function Default Test Features Description Test Mode Register Memory Map AddressMaster Test Register Register 0x400 Master Test Bit Type Function Default Test Mode 0 Details Test Mode 0 Read LocationsPmcatst Boundary Scan 000 Test Mode 0 Write LocationsJtag Test Port Extest Instructions Selected Register Instruction Codes IR20 Identification RegisterBoundary Scan Register Boundary Scan Cells Input PadMUX Bidirectional Cell Iocell Output Cell Outcell Output Enable IocellPAD ATM Mapping into the STS-3c STM-1 SPE Operation Transport Overhead Bytes Transport and Path Overhead Bytes Path Overhead Bytes PAYLOAD5 PAYLOAD6 ATM Cell Data StructurePAYLOAD1 PAYLOAD2 PAYLOAD3 PAYLOAD4 205 Clocking Options Recommended Berm settings Conceptual Clocking Structure Loopback Operation Line Loopback Mode Serial Diagnostic Loopback Mode Parallel Diagnostic Loopback Mode Trstb TCK Control Select Tri-state EnableJtag Support TDO TMS TAP Controller TAP Controller Finite State Machine Capture-DR States Test-Logic-ResetUpdate-DR Run-Test-Idle Bypass Update-IRShift-IR Boundary Scan Instructions Idcode StctestBoard Design Recommendations Power Supply Sequencing Analog Power Supply Filtering Power Sequencing Circuit Interfacing to ECL or Pecl Devices LAN Mode Analog Power Filters with 3.3V Supply Interfacing to ECL or Pecl Initializing the S/UNI-QUAD Using the S/UNI-QUAD with a 5 Volt ODL ATM Utopia Level 2 System Interface Functional Timing Multi-PHY Polling and Addressing Receive Cell Interface 225 Absolute Maximum Ratings Absolute Maximum Ratings TBD 16 D.C. Characteristics Input High Current +10 VIH = VDD. Notes 2 Input Low Current 100 VIL = GND. Notes 1Input High Current +10 VIH = VDD. Notes 1 Input Low Current +10 VIL = GND. Notes 2 Address to Latch Set-up Time Microprocessor Interface Timing Characteristics ALE CSB+RDB Intb TSALW TSALW tHALW TV L TSAW tVWR tHAW ALE CSB+WRB Rstb Pulse Width 100 18 A.C. Timing Characteristics Tenb Hold time to Tfclk Tfclk Frequency MHzTfclk Duty Cycle Tenb Set-up time to Tfclk Transmit ATM System Interface Timing Diagram Renb Hold time to Rfclk Rfclk Frequency MHzRfclk Duty Cycle Renb Set-up time to Rfclk Receive ATM System Interface Timing Diagram RCLK1-4 High to RFPO1-4 Valid Tfpi Set-up Time to Tclk HighTfpi Hold Time to Tclk High Tclk High to Tfpo Valid 239 Jtag Port Interface Timing 241 Theta Ja Theta Jc Ordering and Thermal InformationOrdering Information Thermal Information 243 Mechanical Drawing 304 Pin Super Ball Grid Array Sbga Mechanical Information 245 Web Site Contacting PMC-SIERRA, INCCorporate Information Application Information