Galil DMC-1800 user manual Communication with DMC-1700, Simplified Communications Procedure

Models: DMC-1800 DMC-1700

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Communication with DMC-1700

The DMC-1700 provides four I/O registers beginning at the base address N, where the base address N is set with the address jumpers as described in Ch.2. The Main Communications FIFO register occupies address N and is used for the main communications to the controller (i.e. sending commands and getting data responses). The control register occupies address N+1 and is used for monitoring the status of the main communications. The Secondary FIFO occupies address N+2 and is used for accessing the data record. The Secondary control register at N+3 is used for monitoring the status of the Secondary FIFO.

Communication with DMC-1700

Register

Address

Read/Write

Description

 

 

 

 

 

 

 

 

Main

N

Read and Write

Send commands and receive responses

Communications FIFO

 

 

 

Main Control

N+1

Read and Write

For main FIFO status control

 

 

 

 

Secondary FIFO

N+2

Read and Write

For data record access

 

 

 

 

Secondary Control

N+3

Read and Write

For secondary FIFO status control

 

 

 

 

Simplified Communications Procedure

The simplest approach for communicating with the DMC-1700 is to monitor bits 5 and 6 of the control register at address N+1. Bit 5 is for read status and bit 6 is for write status.

Control Register N+1

Status Bit

Action

Logic State

Meaning

 

 

 

 

5

Read

0

Data to be read

 

 

 

 

5

Read

1

No data to be read

 

 

 

 

6

Read

0

Buffer not full, OK to write

 

 

 

 

6

Read

1

Buffer full. Do not write data

 

 

 

 

Read Procedure-To receive data from the DMC-1700, read the control register at address N+1 and check bit 5. If bit 5 is zero, the DMC-1700 has data to be read in the READ register at address N. Bit 5 must be checked for every character read.

Write Procedure-To send data to the DMC-1700, read the control register at address N+1 and check bit 6. If bit 6 is zero, the DMC-1700 FIFO buffer is not full and 1 character may be written to the register at address N. If bit 6 is one, the buffer is full and no additional data should be written. Bit 6 of N+1 must be checked before every character is written to address N.

Any computer language such as C, Basic, Pascal or Assembly may be used to communicate with the DMC-1700 as long as the READ/WRITE procedure is followed as described above.

Clearing FIFO Buffer-Clearing the FIFO is useful for emergency resets or Abort. For example, to reset the controller, clear the FIFO, then send the RS command to the controller. All data on the FIFO, including data from the DMC-1700, will then be cleared.

The FIFO buffer may be master reset and therefore cleared, by writing the following sequence:

1.Read N+1 address

2.Write 01H to N+1 address

3.Write 80H to N+1 address

4.Write 01H to N+1 address

5.Write 80H to N+1 address

6.Read N+1 address

68 • Chapter 4 - Software Tools and Communications

DMC-1700/1800

Page 76
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Galil DMC-1800 user manual Communication with DMC-1700, Simplified Communications Procedure, Control Register N+1