3-25
3.34: Type F34 Limit and Relay Logic States
QLength: 1 Register (2 bytes)
QThis register has two bytes. Each byte has eight bits. The bits in these bytes are associated with the
16 Limits or Relays, the most significant bit of the most significant byte with Limit 1 (or 17, or
Relay 1), through to the least significant bit of the least significant byte with Limit 16 (or 32, or
Relay 16).
QAbit value of 1 means TRUE, while a bit value of 0 means FALSE. TRUE and FALSE result from
the AND, OR,XOR, Hysteresis and NOT of two input values of 1 or 0.
Example:
Register 05979, Limit States, Combinations, 1 - 16, might contain the following data:
Address
Value
Bytes
Bits
Limit
Logic (T/F)
Interpretation
F
1
00
2
FF
3
00
4
F
0
5
FT
6
10
7
FF
8
00
9
F
1
10
T
1
11
TF
12
00
13
FF
14
0
F
15
01
16
T
Limit Combinations, 6, 10, 11 and 16 are currently TRUE; all others are FALSE.
04H 61H
0461H
05979
3.35: Type F35 Relay Delays
QLength: 1/2 Register (1 byte) (2 per Register)
QThis register has two bytes. Each byte contains an unsigned integer which is a count-down delay. A
relay logic tree must be stable for the duration of the delay before triggering a relay. Delays are
preloaded when the Gate G value changes. They are decremented every pass thereafter, until they
reach zero.
Example:
Register 06000, Delay Timer, Relay 1 / Relay 2, might contain the following data: