6-22
•The next four bytes are a bitmap of the Latched Delta states of the High Speed Limits. For the
first cycle that a limit changes state, the change of state is recognized as a Delta. If waveform
capture parameters require multiple captures for a given change, subsequent captures would be
recognized as having no new Deltas. Therefore, every time a Delta occurs, the new Delta is
latched, so that consecutive captures for the original Delta can still indicate what Delta triggered
the first capture. The order of the bits is the same as for the states of the High Speed Limits, as
above. These bits will only report the changes in limits that are Enabled for PQ Triggering.
•The next byte tells you in which capture to find the trigger. For example, a device records a
surge lasting for two cycles. The surge triggers the first capture and the triggering cycle for the
first capture is in the first capture. However, the cycle which is the subsequent return to normal
is also in the first capture. It triggers the second capture. In the first Trigger Record, this byte
would contain the value 0x000, identifying the triggering sample to be in the first capture, at the
index as given by the above index value. In the second Trigger Record, this byte would also
contain the value 0x000, identifying the triggering sample to also be in the first capture, at the
index and time given by its index value.
•The next two bytes are a signed integer with the index of the sample that was at the end of the
triggering cycle.
•The next 48 bytes are 12 4-byte MSB signed integers representing the RMS values recorded in
the triggering cycle. Following is the order of these readings:
VAN
VBN
VCN
VAUX
IA
IB
IC
IAUX
IN
VAB
VBC
VCA
For a capture in WYE configuration, VAB, VBC and VCA are not computed.
For a capture in DELTAconfiguration, VAN, VBN and VCN are not computed.
Currently, INand IAUXare not computed.