GE EPM 9650/9800 Structure for the Direction and Combination byte, Limit Profile Label Block

The structure for the Direction and Combination byte:

Bits 7-5 Unused, set to 0

Bit 4 Negate combination (AND -> NAND, etc.) Bits 3-2 00 = AND combination

01 = OR combination

10 = XOR combination

11 = Hysteresis combination

Bit 1 0 = second input is not inverted 1 = second input is inverted

Bit 0 0 = first input is not inverted 1 = first input is inverted

Hysteresis combination uses the first input to set the combination, and the second input to clear the combination. If both inputs are asserted, the first input has priority.

Bits 0 and 1, negating inputs, only apply to gates A, B, C and D.

7.30: Limit Profile Label Block (46805-47060)

•Currently, this block is not used.

•8 registers, 16 bytes. 16 characters

7.31: External Analog Output Module Channel Update Block (47061-47062)

This block is added to improve the update speed of what is sent to the External Analog Output Modules from the EPM device. Not all channels of the External Analog Output Module might be in use. The value indicates the number of External Analog Output Module channels that are refreshed per Modbus message. In the older versions of External Analog Output Modules, only one channel update was possible at a time.

	External Analog Output Module Update Speed
Value	Update
0	1 channel at a time
1	2 channels at a time
2	4 channels at a time
3	8 channels at a time
4-255	8 channels at a time

7-18