
C.1.1 UPA
The UltraSPARC port architecture (UPA) provides a
The four address buses are:
UPA address bus 0 (UPA_AD0)
UPA address bus 1 (UPA_AD1)
UPA address bus 2 (UPA_AD2)
UPA address bus 3 (UPA_AD3)
The four data buses are:
UPA data bus 0 (UPA_DATA0)
UPA data bus 1 (UPA_DATA1)
4UPA data bus 2 (UPA_DATA2) UPA data bus 3 (UPA_DATA3)
UPA_AD0 and UPA_AD1 connect the QSC ASIC to the CPU modules and the U2P ASIC. UPA_AD2 connects the QSC ASIC to the U2P ASIC. UPA_AD3 connects the QSC ASIC to the UPA graphics.
Two processor data buses (UPA_DATA0 and UPA_DATA1) are bidirectional
The following table illustrates UPA slot number port addresses.
UPA Slot Number | UPA Port ID <4:0> |
|
|
CPU module slot 0 | 0x0 |
CPU module slot 1 | 01 |
U2P ASIC | 0x1F |
|
|
The following figure shows the data buses functional block diagram.
252 Sun Enterprise 220R Server Service Manual ♦ January 2000, Revision A