PCI-to EBus/Ethernet controller (PCIO)
UPA-to-PCIbridge (U2P)
Frame buffer controller (FBC)
Reset, interrupt, scan, and clock (RISC)
C.1.12.1 XB9+
The XB9+ ASIC is a buffered memory crossbar device that acts as the bridge between
the six system unit buses. The six system unit buses include two processor buses, a
memory data bus, a graphics bus, and two I/O buses. The XB9+ ASIC provides the
following:
Six-port crossbar
Decoupled memory port; loading and unloading of memory data can take place in
parallel with other operations
Burst transfers operate on adoubleword of data per slice
A total of eight two-entry first-in-first-out (FIFO) devices for read data storage
Power-up safe buses (tristated)
C.1.12.2 QSC
The QSC ASIC provides system control. It controls the UPAinterconnect between the
major system unit components and main memory.The QSC ASIC provides the
following:
Interconnect packet receive
Memory arbiter
Non-cached arbiter
Memory controller
Snoop interface
Coherence controller
S_register dispatcher
Internet packet send
Datapatch scheduler
EBus interface
C.1.12.3 PCIO
The PCI-to-EBus/Ethernet controller (PCIO) ASIC performs dual roles: PCI
bus-to-Ebus bridging and Ethernet control. The PCIO ASIC provides the electrical
272 Sun Enterprise 220R Server Service Manual ♦January 2000, Revision A