The preferred signaling protocol is RS-423. The higher voltages of R-232 make it
difficult to switch at the higher baud rates. The maximum rate for RS-232 is
approximately 64 Kbaud while the maximum rate for RS-423 is 460.8 Kbaud. The
system default is set to RS-232.

Synchronous Rates

The serial synchronous ports operate at any rate from 50 Kbaud to 256 Kbaud when
the clock is generated from the serial port controller.When the clock is generated
from an external source, the synchronousports operate at up to 384 Kbaud. Clock
generation is accurate within 1 percent for any rate that is generated between 50
Kbaud and 256 Kbaud.

Asynchronous Rates

The serial asynchronous ports support twenty baud rates that areall exact divisors of
the crystal frequency (with exception for 110, which is off by less than 1 percent).
Baud rates include 50, 75, 110, 200, 300, 600, 1200, 1800, 2400, 4800, 9600, 19200,
38400, 57600, 76800, 115200, 153600, 230400, 307200, and 460800.

Slew Rate and Cable Length

The maximum RS-423 cable length is 118 feet (30 meters) and the maximum RS-232
cable length is 50 feet (15.24 meters). The slew rate changes depending on the speed.
For speeds less than 100 Kbaud, the slew rate is set at 5 VDC per microsecond. For
rates greater than 100 Kbaud, the slew rate is increased to 10 VDC per microsecond.
This allows maximum performance for the greater baud rates and better signal
quality at the lesser baud rates.
C.1.10 Ethernet
The system unit supports 10-Mbps, 10BASE-T, twisted-pair Ethernet and 100-Mbps,
100BASE-TX, media independent interface (MII) Ethernet with the use of a single
magnetics module. Twisted-pair Ethernet is provided through an 8-pin RJ45
connector.MII Ethernet is provided through a 40-pin MII connector.The MII port
allows connection to any cable medium, including unshieldedtwisted-pair (UTP),
shielded twisted-pair (STP), and fiber optic accompanied by the appropriate external
transceiver. Thesystem automatically senses an external transceiver, thus disabling
an on-board transceiver.TheEthernet circuitry design is based on a Quality
Semiconductor PHY.
The PHY chip integrates a 100BASE-TX physical coding sub-layer (PCS) and a
complete 10BASE-T module in a single chip. Itprovides a standard MII to
Functional Description 265