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Freescale Semiconductor MCF5484 Manual
1032 pages 8.48 Mb
2 How to Reach Us:5 Chapter 1 OverviewChapter 2 Signal Descriptions 9 Chapter 3 ColdFire Core10 Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC)Chapter 5 Memory Management Unit (MMU) 11 Chapter 6 Floating-Point Unit (FPU)12 Chapter 7 Local Memory13 Chapter 8 Debug Support14 Chapter 9 System Integration Unit (SIU)15 Chapter 10 Internal Clocks and Bus ArchitectureChapter 11 General Purpose Timers (GPT) 16 Chapter 12 Slice Timers (SLT)Chapter 13 Interrupt Controller 17 Chapter 14 Edge Port Module (EPORT)Chapter 15 GPIO 18 Chapter 16 32-Kbyte System SRAMChapter 17 FlexBus 19 Chapter 18 SDRAM Controller (SDRAMC)21 Chapter 19 PCI Bus Controller23 Chapter 20 PCI Bus Arbiter Module24 Chapter 21 FlexCAN25 Chapter 22 Integrated Security Engine (SEC)27 Chapter 23 IEEE 1149.1 Test Access Port (JTAG)28 Chapter 24 Multichannel DMA30 Chapter 25 Comm Timer Module (CTM)Chapter 26 Programmable Serial Controller (PSC) 33 Chapter 27 DMA Serial Peripheral Interface (DSPI)34 Chapter 28 I2C Interface35 Chapter 29 USB 2.0 Device Controller39 Chapter 31 Mechanical Data41 About This Book59 Chapter 1 Overview71 Chapter 2 Signal Descriptions103 Part I Processor Core150 315 Part II System Integration Unit407 Part III On-Chip Integration409 Chapter 16 32-Kbyte System SRAM417 Chapter 17 FlexBus449 Chapter 18 SDRAM Controller (SDRAMC)18.1 Introduction 18.2 Overview18.2.1 Features 18.2.2 Terminology 18.2.3 Block DiagramFigure 18-1. SDRAM Controller Block Diagram 450 18.3 External Signal Description18.3.1 SDRAM Data Bus (SDDATA[31:0]) 18.3.2 SDRAM Address Bus (SDADDR[12:0]) 18.3.3 SDRAM Bank Addresses (SDBA[1:0]) 18.3.12 SDRAM Clock Enable (SDCKE) 18.3.13 SDR SDRAM Data Strobe (SDRDQS) 18.3.14 SDRAM Memory Supply (SDVDD) 18.3.15 SDRAM Reference Voltage (VREF) 452 18.4 Interface Recommendations457 18.5 SDRAM Overview463 18.6 Functional Overview18.6.1 Page Management 18.6.2 Transfer Size 464 18.7 Memory Map/Register Definition472 18.8 SDRAM ExampleFigure 18-13. SDRAM Configuration Register 2 (SDCFG2) Table 18-13. SDCFG2 Field Descriptions Table 18-14. SDRAM Example Specifications 473 18.8.1 SDRAM Signal Drive Strength SettingsThis configuration results in a value of SDRAMDS = 0x0000_02AA, as described in Table 18-15. 18.8.2 SDRAM Chip Select SettingsTable 18-14. SDRAM Example Specifications (Continued) This configuration results in a value of SDRAMDS = 0x0000_0019, as described in Table 18-16. 474 18.8.3 SDRAM Configuration 1 Register SettingsThis configuration results in a value of SDCFG1 = 0x7362_2830, as described in Table 18-17. The SDCFG1 register should be programmed as shown in Figure 18-16. 475 18.8.4 SDRAM Configuration 2 Register SettingsThe SDCFG2 register should be programmed as shown in Figure 18-17. This configuration results in a value of SDCFG2 = 0x4677_0000, as described in Table 18-18. 18.8.5 SDRAM Control Register Settings and PALL command 477 18.8.6 Set the Extended Mode RegisterThe SDMR should be programmed as shown in Figure 18-19. This step enables the DDR memorys DLL.Figure 18-20. SDRAM Mode/Extended Mode Register Settings (SDMR) This configuration results in a value of SDMR = 0x048D_0000, as described in Table 18-21. This configuration results in a value of SDMR = 0x4001_0000, as described in Table 18-20. 18.8.7 Set the Mode Register and Reset DLLFigure 18-19. SDRAM Mode/Extended Mode Register Settings (SDMR) Table 18-20. SDMR Field Descriptions 478 18.8.8 Issue a PALL commandThis configuration results in a value of SDCR = 0xE10D_0002, as described in Table 18-22.Table 18-21. SDMR Field Descriptions 479 18.8.9 Perform Two Refresh CyclesThis configuration results in a value of SDCR = 0xE10D_0004, as described in Table 18-19.Table 18-22. SDCR + MODE_EN and IPALL Field Descriptions (Continued) 480 18.8.10 Clear the Reset DLL Bit in the Mode RegisterThis configuration results in a value of SDMR = 0x008D_0000, as described in Table 18-21.Figure 18-23. SDRAM Mode/Extended Mode Register Settings Table 18-24. SDMR Field Descriptions Table 18-23. SDCR + MODE_EN and IREF Field Descriptions (Continued) 481 18.8.11 Enable Automatic Refresh and Lock Mode RegisterThis configuration results in a value of SDCR = 0x710D_0F00, as described in Table 18-25.Figure 18-24. SDRAM Control Register Settings + REF Table 18-25. SDCR + REF Field Descriptions Table 18-24. SDMR Field Descriptions (Continued) 482 18.8.12 Initialization Code485 Chapter 19 PCI Bus Controller561 Chapter 20 PCI Bus Arbiter Module20.1 Introduction20.1.1 Block DiagramFigure 20-1. PCI Arbiter Interface Diagram 20.1.2 Overview 20.1.3 Features 562 20.2 External Signal Description20.2.1 Frame (PCIFRM) 20.2.2 Initiator Ready (PCIIRDY) 20.2.3 PCI Clock (CLKIN) 20.2.4 External Bus Grant (PCIBG[4:1]) 20.2.5 External Bus Grant/Request Output (PCIBG0/PCIREQOUT) 20.2.6 External Bus Request (PCIBR[4:1]) 20.2.7 External Request/Grant Input (PCIBR0/PCIGNTIN) 563 20.3 Register Definition20.3.1 PCI Arbiter Control Register (PACR) 20.3.2 PCI Arbiter Status Register (PASR) 565 20.4 Functional Description570 20.5 Reset20.6 Interrupts 571 Chapter 21 FlexCAN603 Chapter 22 Integrated Security Engine (SEC)709 Chapter 23 IEEE 1149.1 Test Access Port (JTAG)719 Part IV Communications Subsystem721 Chapter 24 Multichannel DMA 753 Chapter 25 Comm Timer Module (CTM)763 Chapter 26 Programmable Serial Controller (PSC)26.1 Introduction26.1.1 Block Diagram 26.1.2 Overview 26.1.3 Features 26.1.4 Modes of Operation 764 26.2 Signal Description26.2.1 PSCnCTS/PSCBCLK 26.2.2 PSCnRTS/PSCFSYNC 26.2.3 PSCnRXD 26.2.4 PSCnTXD 26.2.5 Signal Properties in Each ModeThe following table summarizes the signals used for serial communications. 765 26.3 Memory Map/Register Definition26.3.1 Overview 26.3.2 Module Memory MapThe names and address locations of all control registers are listed in Table 26-2. 767 26.3.3 Register Descriptions26.3.3.1 Mode Register 1(PSCMR1n) 768 26.3.3.2 Mode Register 2 (PSCMR2n)770 26.3.3.3 Status Register (PSCSRn)772 26.3.3.4 Clock Select Register (PSCCSRn)Figure 26-5. UART and SIR Baud Rate Clocking Sources Table 26-5. PSCSRn Field Descriptions (Continued) 773 26.3.3.5 Command Register (PSCCRn)776 26.3.3.6 Receiver Buffer (PSCRBn) and Transmitter Buffer (PSCTBn)779 26.3.3.7 Input Port Change Register (PSCIPCRn)PSCIPCRn shows the current state and the change-of-state for the modem control input port.Figure 26-12. Input Port Change Register (PSCIPCRn) Table 26-11. PSCIPCRn Field Descriptions Table 26-10. PSCRBn and PSCTBn AC 97 Mode Field Descriptions 780 26.3.3.8 Auxiliary Control Register (PSCACRn)PSCACR controls the handshake of the transmitter/receiver.Figure 26-14. Interrupt Status Register (PSCISRn) 26.3.3.9 Interrupt Status Register (PSCISRn)Figure 26-13. Auxiliary Control Register (PSCACRn) Table 26-12. PSCACRn Field Descriptions 781 26.3.3.10 Interrupt Mask Register (PSCIMRn)783 26.3.3.11 Counter Timer Registers (PSCCTURn, PSCCTLRn)The PSCIP shows the current state of the input ports. 26.3.3.12 Input Port (PSCIPn)Figure 26-16. Counter Timer Upper Register (PSCCTURn) Table 26-15. PSCCTURn Field Descriptions Table 26-16. PSCCTLRn Field Descriptions Table 26-17. PSCIPn Field Descriptions 784 26.3.3.13 Output Port Bit Set (PSCOPSETn)Output ports are asserted by writing to this register. 26.3.3.14 Output Port Bit Reset (PSCOPRESETn)Output ports are negated by writing to this register. Table 26-18. PSCOPSETn Field Descriptions Table 26-17. PSCIPn Field Descriptions (Continued) 785 26.3.3.15 PSC/IrDA Control Register (PSCSICRn)This register sets the main operation mode. Table 26-20. PSCSICRn Field Descriptions Table 26-21. SIM[2:0] 786 26.3.3.16 Infrared Control Register 1 (PSCIRCR1n)This register controls the configuration in IrDA mode. This register sets some requests to the transmitter or the TxFIFO. 26.3.3.17 Infrared Control Register 2 (PSCIRCR2n)Table 26-22. PSCIRCR1n Field Descriptions Table 26-23. PSCIRCR2n Field Descriptions 787 26.3.3.18 Infrared SIR Divide Register (PSCIRSDRn)26.3.3.19 Infrared MIR Divide Register (PSCIRMDRn)This register sets the baud rate in MIR mode.Table 26-24. PSCIRSDRn Field Descriptions Table 26-23. PSCIRCR2n Field Descriptions (Continued) 788 26.3.3.20 Infrared FIR Divide Register (PSCIRFDRn)This register sets the baud rate in FIR mode.Table 26-25. PSCIRMDRn Field Descriptions Eqn. 26-1 Table 26-26. Frequency Selection in MIR Mode 789 26.3.3.21 Rx and Tx FIFO Counter Register (PSCRFCNTn, PSCTFCNTn)This register applies to all modes. These registers provide access to the internal Rx and Tx FIFOs. 26.3.3.22 Rx and Tx FIFO Data Register (PSCRFDRn, PSCTFDRn)Table 26-27. PSCIRFDRn Field Descriptions Eqn. 26-2 Table 26-28. Frequency Selection in FIR Mode 790 26.3.3.23 Rx and Tx FIFO Status Register (PSCRFSRn, PSCTFSRn)792 26.3.3.24 Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn)794 26.3.3.25 Rx and Tx FIFO Alarm Register (PSCRFARn, PSCTFARn)26.3.3.26 Rx and Tx FIFO Read Pointer (PSCRFRPn, PSCTFRPn)Table 26-31. PSCRFCRn and PSCRTFCRn Field Descriptions (Continued) 795 26.3.3.27 Rx and Tx FIFO Write Pointer (PSCRFWPn, PSCTFWPn)26.3.3.28 Rx and Tx FIFO Last Read Frame Pointer (PSCRLRFPn, PSCTLRFPn) 796 26.3.3.29 Rx and Tx FIFO Last Write Frame Pointer (PSCRLWFPn, PSCTLWFPn)797 26.4 Functional Description809 26.5 Resets26.5.1 General 26.5.2 Description of Reset Operation26.5.2.1 Reset 26.5.2.2 CRSRX 26.5.2.3 CRSTX 26.5.2.4 CRSES 810 26.6 Interrupts26.6.1 Description of Interrupt Operation 26.6.1.1 Processor Interrupt 26.7 Software Environment26.7.1 General 811 26.7.2 Configuration26.7.2.1 UART ModeThe following is a sample initialization sequence for UART mode. Table 26-41. Sample Initialization Sequence for UART Mode 812 26.7.2.2 Modem8 ModeTable 26-42. Sample Initialization Sequence for Modem8 Mode Table 26-41. Sample Initialization Sequence for UART Mode (Continued) 813 26.7.2.3 Modem16 Mode26.7.2.4 AC97 ModeTable 26-43. A Sample Initialization Sequence for AC97 Mode Table 26-42. Sample Initialization Sequence for Modem8 Mode (Continued) 814 26.7.2.5 SIR ModeHere is a sample configuration sequence in SIR mode. Table 26-44. A Sample Initialization Sequence for SIR Mode Table 26-43. A Sample Initialization Sequence for AC97 Mode (Continued) 815 26.7.2.6 MIR ModeTable 26-45. A Sample Initialization Sequence for MIR Mode Table 26-44. A Sample Initialization Sequence for SIR Mode (Continued) 816 26.7.2.7 FIR ModeTable 26-46. A Sample Initialization Sequence for FIR Mode Table 26-45. A Sample Initialization Sequence for MIR Mode (Continued) 817 26.7.3 Programming26.7.3.1 MIR ModeTable 26-46. A Sample Initialization Sequence for FIR Mode (Continued) 818 26.7.3.2 FIR Mode 819 Chapter 27 DMA Serial Peripheral Interface (DSPI)855 Chapter 28 I2C Interface875 Chapter 29 USB 2.0 Device Controller931 Chapter 30 Fast Ethernet Controller (FEC)991 Chapter 31 Mechanical Data1011 Appendix A MCF548x Memory MapTable A-1 lists an overview of the memory map for the on-chip modules. 1015 Index
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