MCF548x Reference Manual, Rev. 3
29-38 Freescale Semiconductor

29.2.5.4 USB Endpoint n FIFO RAM Configuration Register (EPnFRCFGR)

The EPnFRCFGR allows the software to allocate the total FIFO RAM space among the individual

endpoint FIFOs. Note that care should be taken to ensure that no two active endpoints are allocated to the

same memory address range, as this will result in corrupted data.

Table 29-38. EPnIMR Field Descriptions

Bits Name Description
31–9 — Reserved, should be cleared.
8 FU FIFO full. This bit enables FIFO Full interrupts.
0 FIFO FULL interrupts enabled.
1 FIFO FULL interrupts disabled.
7 EMT FIFO empty. This bit enables FIFO Empty interrupts.
0 FIFO EMPTY interrupts enabled.
1 FIFO EMPTY interrupts disabled.
6 ERR FIFO error. This bit enables FIFO error interrupts.
0 FIFO ERROR interrupts enabled.
1 FIFO ERROR interrupts disabled.
5 FIFOHI FIFO high. This bit enables FIFO High interrupts.
0 FIFO HIGH interrupts enabled.
1 FIFO HIGH interrupts disabled.
4 FIFOLO FIFO low. This bit enables FIFO Low interrupts.
0 FIFO LOW interrupts enabled.
1 FIFO LOW interrupts disabled.
3 — Reserved, should be cleared.
2 EOT End of transfer. This bit enables end of transfer interrupts.
0 End of transfer indicator interrupts enabled.
1 End of transfer indicator interrupts disabled.
1 — Reserved, should be cleared.
0 EOF End of frame. This bit enables end of frame interrupts.
0 End of frame indicator interrupts enabled.
1 End of frame indicator interrupts disabled.