Freescale Semiconductor 18.5.1.1 Row and Bank Active Command (ACTV), 18.5.1.2 Read Command (READ), 18.5.1.3 Write Command (WRITE)

MCF548x Reference Manual, Rev. 3
18-10 Freescale Semiconductor
Many commands require a delay before the next command may be issued; sometimes the delay depends
on the type of the next command. These delay requirements are managed by the values programmed in the
memory controller configuration registers (SDCFG1, SDCFG2).
18.5.1.1 Row and Bank Active Command (ACTV)
The ACTV command is responsible for latching the row and bank address and activating the specified row
in the memory array. Once the row is activated, it can be accessed using subsequent READ and WRITE
commands.
NOTE
The SDRAMC will support one active row for each chip select block. See
Section 18.6.1, “Page Management” for more information.
18.5.1.2 Read Command (READ)
When the SDRAMC receives a read request, it first checks the row and bank of the new access. If the
address falls within the active row of an active bank, it is a page hit, and the READ is issued as soon as
possible (pending any delays required by previous commands). If the address is within the active row, but
the needed bank is inactive, or if there is no active row, the memory controller will issue an ACTV
followed by the READ command. If the address is not within the active row, the memory controller will
issue a PALL command to close the active row. Then the SDRAMC issues ACTV to activate the necessary
bank and row for the new access, followed finally by the READ to the SDRAM.
The PALL and ACTV commands (if necessary) can sometimes be issued in parallel with an on-going data
movement.
All reads, whether burst or single, must be allowed to complete the entire burst length on the memory bus.
With SDR memory, the data masks are negated throughout the entire read burst length. With DDR
memory, the data masks are asserted throughout the entire read burst length; but DDR memory ignores the
data masks during reads.
18.5.1.3 Write Command (WRITE)
When the memory controller receives a write request, it first checks the row and bank of the new access.
If the address falls within the active row of an active bank, it is a page hit, and the WRITE is issued as soon
as possible (pending any delays required by previous commands). If the address is within the active row
but the needed bank is inactive, or if there is no active row, the memory controller will issue an ACTV
followed by the WRITE command. If the address is not within the active row, the memory controller will
Self-Refresh SREF H→LLLLH X X X
Power-Down PDWN H→LHXXX X X X
H = High
L = Low
V = Valid
X = Don’t care
Table 18-3. SDRAM Commands (Continued)
Function Symbol CKE CS RAS CAS WE BA[1:0] AP/C
MD Other A