MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 7-1

Chapter 7

Local Memory

This chapter describes the MCF548x implementation of the ColdFire Version 4e local memory
specification. It consists of two major sections.
•Section 7.2, “SRAM Overview,” describes the MCF548x core’s local static RAM (SRAM)
implementation. It covers general operations, configuration, and initialization. It also provides
information and examples showing how to minimize power consumption when using the SRAM.
•Section 7.7, “Cache Overview,” describes the MCF548x cache implementation, including
organization, configuration, and coherency. It describes cache operations and how the cache
interfaces with other memory structures.

7.1 Interactions between Local Memory Modules

Depending on configuration information, instruction fetches and data read accesses may be sent
simultaneously to the SRAM and cache controllers. This approach is required because all three controllers
are memory-mapped devices, and the hit/miss determination is made concurrently with the read data
access. Power dissipation can be minimized by configuring the RAMBARs to mask unused address spaces
whenever possible.
If the access address is mapped into the region defined by the SRAM (and this region is not masked), the
SRAM provides the data back to the processor, and the cache data is discarded. Accesses from the SRAM
module are never cached. The complete definition of the processor’s local bus priority scheme for read
references is as follows:
if (SRAM “hits”)
SRAM supplies data to the processor
else if (data cache “hits”)
data cache supplies data to the processor
else system memory reference to access data
For data write references, the memory mapping into the local memories is resolved before the appropriate
destination memory is accessed. Accordingly, only the targeted local memory is accessed for data write
transfers.
NOTE
The two SRAMs discussed in this chapter is on the processor local bus.
There is a third 32-Kbyte SRAM on the MCF548x device. See Chapter 16,
“32-Kbyte System SRAM,” for more information.

7.2 SRAM Overview

The two 4-Kbyte, on-chip SRAM modules provide the core with pipelined, single-cycle access to memory.
Memory can be independently mapped to any 0-modulo-4K location in the 4-Gbyte address space and
configured to respond to either instruction or data accesses.
The following summarizes features of the MCF548x SRAM implementation:
• Two 4-Kbyte SRAMs, organized as 1024 x 32 bits
• Single-cycle throughput. When the pipeline is full, one access can occur per clock cycle.