Interface Recommendations
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 18-5

All memory devices of a single chip select block must have the same configuration and row/col address

width; however, this is not necessary between different blocks. If mixing different memory organizations

in different blocks, the following guidelines will ensure that every block is fully contiguous.

• If all devices’ row address width is 12 bits, the column address can be ≥ 8 bits.

• If all devices’ row address width is 13 bits, the column address can be ≥ 8 bits.

• If all devices’ column address width is 8 bits, the row address can be ≥ 11 bits.

• x8 and x16 data width memory devices can be mixed (but not in the same space).

• x32 data width memory devices cannot be mixed with any other width.

Table 18-2. SDRAM Address Multiplexing

Device Configur
ation
Row bit x
Col bit x
Bank bit
Number
of
Devices
Total
Block
Size
SDCR
[MUX]
Setting
Internal Address
27 26 25 24 23–12 11–10 9���2
64 Mbits
512K x 32 bit 11 x 8 x 2 1 8 MB 00 — — — —
RA11-0 BA1-0 CA7-0
4M x 16 bit 12 x 8 x 2 2 16 MB 00 — — — —
8M x 8bit
12 x 9 x 2
432 MB
00 — — — CA8
13 x 8 x 2 01 — — — RA12
16M x 4 bit
12 x 10 x 2
864 MB
00 — — CA9 CA8
13 x 9 x 2 01 — — CA8 RA12
128
Mbits
4M x 32 bit 12 x 8 x 2 1 16 MB 00 — — — —
RA11-0 BA1-0 CA7-0
8M x 16 bit
12 x 9 x 2 232 MB
00 — — — CA8
13 x 8 x 2 01 — — — RA12
16M x 8 bit
12 x 10 x 2
464 MB
00 — — CA9 CA8
13 x 9 x 2 01 — — CA8 RA12
32M x 4 bit
12 x 11 x 2
8128
MB
00 — CA11 CA9 CA8
13 x 10 x 2 01 — CA9 CA8 RA12
256
Mbits
16M x 16 bit
12 x 10 x 2
264 MB
00 — — CA9 CA8
RA11-0 BA1-0 CA7-0
13 x 9 x 2 01 — — CA8 RA12
32M x 8 bit
12 x 11 x 2
4128
MB
00 — CA11 CA9 CA8
13 x 10 x 2 01 — CA9 CA8 RA12
64M x 4 bit
12 x 12 x 2
8256
MB
00 CA12 CA11 CA9 CA8
13 x 11 x 2 01 CA11 CA9 CA8 RA12
512
Mbits
32M x 16 bit
12 x 11 x 2
2128
MB
00 — CA11 CA9 CA8
RA11-0 BA1-0 CA7-0
13 x 10x 2 01 — CA9 CA8 RA12
64M x 8bit
12 x 12 x 2
4256
MB
00 CA12 CA11 CA9 CA8
13 x 11 x 2 01 CA11 CA9 CA8 RA12