MCF548x Reference Manual, Rev. 3
17-14 Freescale Semiconductor

4. FBCSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would

be an idle clock between cycles to provide hold time for address, attributes, and write data.

17.6.4.1 Data Transfer Cycle States

The data transfer operation in the MCF548x is controlled by an on-chip state machine. The state transition

diagram for basic read and write cycles is shown in Figure 17-7.

Figure 17-7. Data Transfer State Transition Diagram

Table 17-11 describes the states as they appear in subsequent timing diagrams.

Table 17-11. Bus Cycle States

State Cycle Description
S0 All The read or write cycle is initiated. On the rising clock edge, the MCF548x places a valid address
on AD[31:0], asserts ALE, and drives R/W high for a read and low for a write, if these signals are
not already in the appropriate state.
S1 All ALE is negated on the rising edge of CLK, and FBCSn is asserted. Data is driven on AD[31:Y] for
writes, and AD[31:Y] is three-stated for reads. Address continues to be driven on AD[X:0] pins that
are unused for data.
If TA is recognized asserted, then the cycle moves on to S2. If TA is not asserted either internally
or externally, then the S1 state continues to repeat.
Read Data is made available by the external device before the rising edge of CLK with TA asserted. The
the MCF548x will latch data on this rising clock edge.
S2 All For internal termination, both the FBCSn and internal TA will be negated. For external termination,
the external device should negate TA, and FBCSn select is negated after the rising edge of CLK at
the end of S2.
Read The external device can stop driving data after the rising edge of CLK at the beginning of S2.
However, data can be driven until the end of S3 or any additional address hold cycles.
S3 All Address, data, and R/W go invalid off the rising edge of CLK at the end of S3, terminating the read
or write cycle.
S0
S1
S2
Wait States
S3
Next Cycle