Freescale Semiconductor 24.4.9 Line Buffers

MCF548x Reference Manual, Rev. 3
24-26 Freescale Semiconductor
24.4.9 Line Buffers
The multichannel DMA makes use of line buffers in its interface to the XL bus to combine writes and to
prefetch reads to increase performance. Each line buffer is 32 bytes in depth.
The buffer interface has two queues, one for prefetched reads, and another for collecting writes. There are
two line buffers in the write queue. Each buffer keeps byte validity, and has a tag address valid on the line
boundary. There are four read line buffers. Each of these buffers has a line address and keeps longword
validity. The default behavior of this interface during data transfer is governed by settings in the task table,
the combine write enable bit (CW) and the read line enable bit (RL). When the MDE is fetching task code,
it functions as if the read line enable bit is asserted even if it is not. It will also combine writes when
appropriate.
24.4.9.1 Combine Write Enable
The assertion of this bit turns on the capability to collect writes into a line buffer. When asserted, all writes
to the same line address will be written into a line buffer until
1. a write to a different line address is encountered,
2. the buffer is instructed to flush,
3. a write occurs to a byte that is already valid in the line buffer, or
4. the combine write enable bit is deasserted.
If any of these four events occurs, the current line buffer will be “flushed.” The contents of the buffer will
be partitioned into the largest possible transfer sizes and then written one by one.
The DMA will instruct the line buffers to flush (case 2 above) when asserting an interrupt, switching tasks,
completing a task, or after saving context even if there is not an immediate task switch.
When the combine write enable signal is not asserted, the first write data will post into one of the write
queue buffers and the buffer will be tagged as “busy.” Assuming there is no pending read transaction on
the XL bus, an XL bus write transaction will be immediately initiated using the data in the write queue.
When the write transaction on the XL bus is complete, the busy tag will be removed from the write queue
buffer. During the time that the first write queue buffer is busy, no more writes can be posted to that buffer.
However, a subsequent write can be posted to the second write queue buffer after which that buffer will be
tagged as busy. While both write queue buffers are busy, all write requests from the DMA will incur wait
states.
24.4.9.2 Read Line Enable
The assertion of this bit turns on the capability to prefetch read accesses by fetching an entire line of data
for each read access. Once the data has been prefetched, subsequent accesses to data in the same line
address as the first read will be acknowledged with data from the prefetch buffer.
24.4.9.3 Speculative Prefetch
The assertion of the SP bit in tandem with the assertion of the RL bit results in speculative reads on the XL
bus to fill all four read queue buffers. A speculative read transaction will be initiated when there is no other
pending XL read/write requests and the DMA is reading from an address that is already buffered in the
read queue. If the RL bit is not asserted for the task, the SP bit has no effect.