Functional Overview
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 18-15
8. Issue a second PALL command. Initialize the SDRAM control register (SDCR) with
SDCR[IPALL] set. The SDCR[REF, and IREF] bits should remain cleared for this step.
9. Refresh the SDRAM. The SDRAM spec should indicate a number of refresh cycles to be
performed before issuing an LMR command. Write to the SDCR with the IREF bit set
(SDCR[MODE_EN, REF, and IPALL] should be cleared). This will force a refresh of the
SDRAM each time the IREF bit is set. Repeat this step until the specified number of refresh
cycles have been completed.
10. Initialize the SDRAM’s mode register using the LMR command. See Section 18.5.1.5, “Load
Mode/Extended Mode Register Command (LMR, LEMR)” for more instruction on issuing an
LMR command. During this step the OP_MODE field of the mode register should be set to
“normal operation.”
11. Set SDCR[REF] to enable automatic refreshing, and clear SDCR[MODE_EN] to lock the SDMR.
SDCR[MODE_EN, IREF, and IPALL] remain cleared.

18.6 Functional Overview

18.6.1 Page Management

SDRAM devices have four internal banks. A particular row and bank of memory must be activated to
allow read and write accesses. The SDRAM controller supports paging mode to maximize the memory
access throughput. During operation, the SDRAM controller maintains an open page address for each
SDCS block. An open page is composed of the active rows in the internal banks.
SDRAMs can have a different row address open in each bank, but the SDRAMC does not support this.
The page size of a SDCS block is equal to the space size divided by the number of rows; but the page may
not be contiguous in the XLB address space because the internal address bits used for memory column
address [11:8] and column address [7:0] are not consecutive.
Because the column address may be split across two portions of the XLB address, the contiguous page size
is (number of banks) × (256 columns) × (number of bits). This gives a contiguous page size of 4 Kbytes.
However, the total (possibly fragmented) page size is (number of banks) × (number of columns) × (number
of bits).
If a new access does not fall in the open page of a SDCS block, the open page must be closed (PALL) and
the new page must be opened (ACTV), then the READ or WRITE command can proceed. An ACTV
command only activates one bank of a page. If another read or write falls in an inactive bank of the open
page, another ACTV is needed but no precharge is needed. If a read or write falls in any of the active banks
of the open page, no PALL or ACTV is needed; the read or write command can be issued immediately.
A page is kept open until one of the following conditions occurs:
• an access outside the open page
• a refresh cycle is started.
All SDCS blocks are refreshed at the same time; the refresh closes all banks of every SDRAM block.

18.6.2 Transfer Size

In the MCF548x, the internal data bus is 64 bits wide, while the SDRAM external interface bus is 32 bits
wide. Therefore, each XLB data beat requires two memory data beats. The SDRAM controller manages
the size translation (packing/unpacking) between 64- and 32-bit buses.