MCF548x Reference Manual, Rev. 3
27-20 Freescale Semiconductor
State transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or
on the next system clock cycle if no transfers are in progress.

27.7.2 Serial Peripheral Interface (SPI)

The SPI transfers data serially using a shift register and a selection of programmable transfer attributes.
The SPI frames can be from 4 to 16 bits long. The data to be transmitted can come from queues stored in
RAM external to the DSPI. Host software or the DMA controller can transfer the SPI data from the queues
to a FIFO. The received data is stored in entries in the receive FIFO (Rx FIFO) buffer. Host software or
the DMA controller transfer the received data from the Rx FIFO to memory external to the DSPI. The
FIFO buffer operations are described in Section 27.7.2.4, “Tx FIFO Buffering Mechanism” and
Section 27.7.2.5, “Rx FIFO Buffering Mechanism.” The interrupt and DMA request conditions are
described in Section 27.7.6, “Interrupts/DMA Requests.”
The SPI supports two block-specific modes: master mode and slave mode. The FIFO operations are similar
for both modes. The main difference is that in master mode the DSPI initiates and controls the transfer
according to the fields in the SPI command field of the Tx FIFO entry. In slave mode, the DSPI only
responds to transfers initiated by a bus master external to the DSPI, and the SPI command field of the Tx
FIFO entry is ignored.

27.7.2.1 Master Mode

In SPI master mode, the DSPI initiates the serial transfers by controlling the serial communications clock
(DSPISCK) and the peripheral chip select (DSPICSn) signals. The SPI command field in the executing Tx
FIFO entry determines which DCTAR register will be used to set the transfer attributes and which
DSPICSn signals to assert. The command field also contains various bits that help with queue management
and transfer protocol. See Section 27.6.6, “DSPI Tx FIFO Register (DTFR)” for details on the SPI
command fields. The data field in the executing Tx FIFO entry is loaded into the shift register and shifted
out on the serial out (DSPISOUT) pin. In SPI master mode, each SPI frame to be transmitted has a
command associated with it, allowing for transfer attribute control on a frame-by-frame basis.

27.7.2.2 Slave Mode

In SPI slave mode, the DSPI responds to transfers initiated by an SPI bus master. The DSPI does not
initiate transfers. Certain transfer attributes such as clock polarity, clock phase, and frame size must be set
Table 27-14. State Transitions for Start and Stop of DSPI Transfers
Transition # Current State Next State Description
0 Reset Stopped Generic power-on-reset transition
1 Stopped Running The DSPI is started (DSPI transitions to Running) when all of the following
conditions are true:
• EOQF bit is clear
• Debug mode is unselected or the FRZ bit is clear
• HALT bit is clear
2 Running Stopped The DSPI stops (transitions from Running to Stopped) after the current frame
for any one of the following conditions:
• EOQF bit is set
• Debug mode is selected and the FRZ bit is set
• HALT bit is set