MCF548x Reference Manual, Rev. 3
7-10 Freescale Semiconductor

7.9 Cache Operation

Figure 7-5 shows the general flow of a caching operation using the 32-Kbyte data cache as an example.
The discussion in this chapter assumes a data cache. Instruction cache operations are similar except that
there is no support for writing to the cache; therefore, such notions of modified cache lines and write
allocation do not apply.
Figure 7-5. Data Caching Operation
The following steps determine if a data cache line is allocated for a given address:
1. The cache set index, A[12:4], selects one cache set.
2. A[31:13] and the cache set index are used as a tag reference or are used to update the cache line
tag field. Note that A[31:13] can specify 19 possible address lines that can be mapped to one of
the four ways.
3. The four tags from the selected cache set are compared with the tag reference. A cache hit occurs
if a tag matches the tag reference and the V bit is set, indicating that the cache line contains valid
data. If a cacheable write access hits in a valid cache line, the write can occur to the cache line
without having to load it from memory.
If the memory space is copyback, the updated cache line is marked modified (M = 1), because the
new data has made the data in memory out of date. If the memory location is write-through, the
write is passed on to system memory and the M bit is never used. Note that the tag does not have
TT or TM bits.
To allocate a cache entry, the cache set index selects one of the cache’s 512 sets. The cache control logic
looks for an invalid cache line to use for the new entry. If none is available, the cache controller uses a
034121331
Index
Tag Data/Tag Reference
MUX
Comparator 0
1
2
3
Logical OR
Hit 3
Hit 2
Hit 1
Hit 0
Hit
Line Select
Set 0
Set 1
Set 511
•
•
•
Address
A[31:13]
Way 0
Way 1
Way 2
Way 3
TAG STATUSLW0LW1LW2LW3
TAG STATUS LW0 LW1 LW2 LW3
•
•
••
•
••
•
••
•
••
•
••
•
•
Address
Set
Select
A[12:4]
Data