MCF548x Reference Manual, Rev. 3
5-20 Freescale Semiconductor
Figure 5-10 shows more details of the MMU structure. The TLB is accessed at the beginning of the KC1
pipeline stage so the resulting physical address can be sourced to the cache controllers to factor into the
cache hit/miss determination. This is required because caches are virtually indexed but physically mapped.
Figure 5-10. Address and Attributes Generation

5.6 MMU Implementation

The MMU implements a 64-entry full-associative Harvard TLB architecture with 32-entry ITLB and
DTLB. This section provides more details of this specific TLB implementation. This section details the
operation and looks at the size, frequency, miss rate, and miss recovery time of this specific TLB
implementation.

5.6.1 TLB Address Fields

Because the TLB has a total of 64 entries (32 each for the ITLB and DTLB), a 6-bit address field is
necessary. TLB addresses 0–31 reference the ITLB, and TLB addresses 32–63 reference the DTLB.
In the MMUOR, bits 0 through 5 of the TLB allocation address (AA[5–0]) have this address format for
CF4e. The remaining TLB allocation address bits (AA[15–6]) are ignored on updates and always read as
zero.
JADDR, J Control
TLB Hit
KADDR_KC1
entries
Comp
TLB tag entries
TLB data
entry
TLB hit
data
KC1
J
Memory unit access control
(MMUBAR, RAMBARs, ROMBARs,
ACRs, CACR priority hit logic)
Translated address
MMU’s access control
Untranslated address
mapping register’s
access control
KC1 cycle access control
Mapping register hit
or special mode access
To memory controllers
To control for TLB miss
logic
To control for TLB miss
logic
To memory controllers plus
bus interface