Freescale Semiconductor 19.4.6.1 Access Width, 19.4.6.2 Addressing

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 19-67
on the XL bus will have 100% bandwidth available to them during PCI multichannel DMA activities. In
general, this block will be used by functions in the multichannel DMA API.
The communication subsystem initiator interface consists of Receive and Transmit FIFOs, integrated as
separate multichannel DMA peripherals. Therefore, it is generally controlled by the multichannel DMA
controller through a pre-described program loop. As with all communication subsystem peripherals, it can
be accessed and controlled directly through the slave bus interface if desired, but this path does not
generally lend itself to high throughput.
The Transmit and Receive FIFOs are 32 × 36 bits and support PCI bursts up to 8 beats. This burst size is
programmable. The general approach is to write a PCI command and address to the control register along
with the number of bytes to be transmitted (Packet_Size).
When transmitting data, the module will wait for the Transmit FIFO to fill and then begin transmitting the
data onto the PCI bus. Multichannel DMA must handle filling the Transmit FIFO to support the specified
number of bytes. Transmission will continue until the specified number of bytes have been sent.
When reading data, the module will check that enough space is available in the Receive FIFO and
immediately begin PCI read transactions. Multichannel DMA must handle emptying the Receive FIFO to
support the specified number of bytes. Transmission will continue until the specified number of bytes have
been received.
At this point, software must restart the procedure by at least re-writing the Packet_Size register. Each
transmission of the specified number of bytes is considered a “packet”. A new packet can be instructed to
continue at the last valid PCI address or software may choose to write a new starting address. The largest
burst size is 8 and the largest Packet_Size is 65,532, so a packet will typically consist of many PCI data
bursts.
The Transmit Controller will wait until sufficient bytes are in the Transmit FIFO to support a full burst and
will continue in this mode until the entire packet is transmitted. Similarly, the Receive Controller will stall
until sufficient space is available in the Receive FIFO to support a full burst. If the packet is nearly done
and the number of bytes remaining to complete the packet is less than Max_beats, the remaining data will
be performed as single-beat PCI transactions.
19.4.6.1 Access Width
This multichannel DMA module primarily performs 32-bit data accesses to and from PCI, even though
some signals are referred to in bytes. The two least significant bits of the PCITPSR and PCIRPSR value
are ignored. All PCI byte enables are enabled during these types of accesses. Additionally, the FIFOs
should only be accessed using 32-bit accesses.
The communication subsystem interface optionally supports 16 bit accesses on the PCI bus. Because reads
and writes to and from the FIFO require 32-bit accesses, using this option requires padding the remaining
16 bits of data.
19.4.6.2 Addressing
The communication subsystem initiator interface does not use the addressing windows that are set up for
the XL bus initiator interface. Instead, the Tx Start Address register and Rx Start Address register are used.
Software programs these registers with the initial starting address for the packet. The module contains an
internal counter which will present the incremented PCI address at the beginning of each successive burst
for packet transfers.
If the Disable Increment bit is set, the PCI controller will present the same address during the address phase
of each PCI transaction throughout the entire packet transmission.