MCF548x Reference Manual, Rev. 3
7-20 Freescale Semiconductor
28 DDPI Disable CPUSHL invalidation.
0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified, then
invalidated.
1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified, then
left valid.
27 DHLCK Half-data cache lock mode
0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache
allocates the way pointed at by the counter and then increments this counter.
1 Half-cache operation. The cache allocates to the lower invalid way of levels 2 and 3; if both are
valid, the cache allocates to Way 2 if the high-order bit of the round-robin counter is zero;
otherwise, it allocates Way 3 and increments the round-robin counter. This locks the contents of
ways 0 and 1. Ways 0 and 1 are still updated on write hits and may be pushed or cleared by
specific cache push/invalidate instructions.
26–25 DDCM Default data cache mode. For normal operations that do not hit in the RAMBARs, ROMBARs, or
ACRs, this field defines the effective cache mode.
00 Cacheable write-through imprecise
01 Cacheable copyback
10 Cache-inhibited precise
11 Cache-inhibited imprecise
Precise and imprecise accesses are described in Section 7.9.1.2, “Cache-Inhibited Accesses.”
24 DCINVA Data cache invalidate all. Writing a 1 to this bit initiates entire cache invalidation. Once invalidation
is complete, this bit automatically returns to 0; it is not necessary to clear it explicitly. Note the caches
are not cleared on power-up or normal reset, as shown in Figure 7-4.
0 No invalidation is performed.
1 Initiate invalidation of the entire data cache. The cache controller sequentially clears V and M bits
in all sets. Subsequent data accesses stall until the invalidation is finished, at which point, this bit
is automatically cleared. In copyback mode, the cache should be flushed using a CPUSHL
instruction before setting this bit.
23 DDSP Data default supervisor-protect. For normal operations that do not hit in the RAMBAR, ROMBAR,
or ACRs, this field defines supervisor-protection
0 Not supervisor protected
1 Supervisor protected. User operations cause a fault
22–20 — Reserved, should be cleared.
19 BEC Enable branch cache.
0 Branch cache disabled. This may be useful if code is unlikely to be reused.
1 Branch cache enabled.
18 BCINVA Branch cache invalidate. Invalidation occurs when this bit is written as a 1. Note that branch caches
are not cleared on power-up or normal reset.
0 No invalidation is performed.
1 Initiate an invalidation of the entire branch cache.
17–16 — Reserved, should be cleared.
15 IEC Enable instruction cache
0 Instruction cache disabled. All instructions and tags in the cache are preserved.
1 Instruction cache enabled.
14 — Reserved, should be cleared.

Table 7-4. CACR Field Descriptions (Continued)

Bits Name Description