Freescale Semiconductor 30.3.3.20 FEC Receive FIFO Control Register (FECRFCR)

MCF548x Reference Manual, Rev. 3
30-28 Freescale Semiconductor
30.3.3.20 FEC Receive FIFO Control Register (FECRFCR)
The FIFO receive control register provides programmability of FIFO behaviors, including last transfer
granularity and frame operation. Last transfer granularity allows the user to control when the FIFO
controller stops requesting data transfers through the FIFO alarm by modifying the clearing point of the
alarm, ensuring the data stream is stopped at a valid point, or there remains enough space in the FIFO to
unload the input data pipeline. Additional explanation of this field can be found below. The frame enable
(FRMEN) bit of the control register provides a capability to enable and control the FIFO controller’s
ability to view data on a packetized basis. Frame mode overrides the FIFO granularity bits. The bits of this
register are shown in Figure 30-23, and the fields are further defined in the field descriptions in
Table 30-27.
21 UF FIFO underflow. This bit signifies the read pointer has surpassed the write pointer. If not masked, a
one in this bit will cause a RFERR in the EIR. This bit will remain set until a 1 is written to this bit
location.
0 No FIFO underflow.
1 Signifies an underflow condition in the FIFO.
20 OF FIFO Overflow. This bit signifies the write pointer has surpassed the read pointer. If not masked, the
assertion of this bit will cause a RFERR in the EIR. This bit will remain set until a 1 is written to this
bit location.
0 No FIFO overflow.
1 Signifies an overflow condition in the FIFO.
The FEC cannot overflow the FIFO because wait states will be inserted instead.
19 FRMRDY Frame ready. This read only bit indicates that there is framed data ready. All complete frames must
be read from the FIFO to clear this bit. This bit will only be set while in frame mode.
18 FU Full. This read only bit indicates that the FIFO is full. The FIFO must be read to clear this bit.
17 ALARM Alarm. This read only bit indicates that the FIFO has determined an alarm condition.When the FIFO
is configured to receive, the FIFO alarm provides high level indication, setting when there are less
than alarm bytes free in the FIFO (see Section 30.3.3.23, “FEC Receive FIFO Alarm Register
(FECRFAR),” for more information). The alarm is cleared when the FIFO is read so that fewer than
FECRFCR[GR] bytes remaining in the FIFO.
16 EMT Empty. This read only bit indicates that the FIFO is empty. The FIFO must be written to clear this bit.
15–0 — Reserved, should be cleared.
Table 30-26. FECRFSR Field Descriptions (Continued)
Bits Name Descriptions