MCF548x Reference Manual, Rev. 3
26-30 Freescale Semiconductor

26.3.3.24 Rx and Tx FIFO Control Register (PSCRFCRn, PSCTFCRn)

The FIFO control registers provide programmability of FIFO behaviors, including last transfer granularity
and frame operation. Last transfer granularity allows the user to control when the FIFO controller stops
requesting data transfers through the FIFO alarm by modifying the clearing point of the alarm, ensuring
the data stream is stopped at a valid point, or there remains enough space in the FIFO to unload the input
data pipeline. Additional explanation of this field can be found below. The frame bit of the control register
provides a capability to enable and control the FIFO controller’s ability to view data on a packetized basis.
Frame mode overrides the FIFO granularity bits, by setting the PSCRFSR[FRMRDY] bit. The bit
definitions for this register are shown in Figure 26-21, and the fields are further defined in the field
description below.
This register applies to all modes.
2 FU FIFO full alarm. This read only bit indicates that the FIFO is full. The FIFO must be read to clear this
alarm.
0 FIFO is not full.
1 FIFO has requested attention because it is full. The FIFO must be read to clear this alarm.
1 ALARM Alarm. This read-only bit indicates that the FIFO has determined an alarm condition.
For Transmitter: The FIFO alarm provides a low level indication, setting when there are less than
alarm bytes in the FIFO (see Section 26.3.3.25, “Rx and Tx FIFO Alarm Register (PSCRFARn,
PSCTFARn)” for more information). The alarm is cleared when the FIFO is written so that less than
( 4 × PSCTFCR[GR]) free bytes in the FIFO.
For Receiver: The FIFO alarm provides a high level indication, setting when there are more than
alarm bytes free in the FIFO (see Section 26.3.3.25, “Rx and Tx FIFO Alarm Register (PSCRFARn,
PSCTFARn)” for more information). The alarm is cleared when the FIFO is read so that fewer than
PSCRFCR[GR] bytes remain in the FIFO.
0 Alarm not set.
1 FIFO has requested attention because it has determined an alarm condition.
0 EMT FIFO empty. This read only bit indicates that the FIFO is empty. The FIFO must be written to clear
this bit.
0 FIFO not empty.
1 FIFO has requested attention because it is empty. The FIFO must be written to clear this alarm.
Table 26-30. PSCRFSRn and PSCTFSRn Field Descriptions (Continued)
Bits Name Description