Suggested Reading
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor xliii
—Chapter 21, “FlexCAN,” describes the MCF548 implementation of the controller area network
(CAN) protocol. This chapter describes FlexCAN module operation and provides a
programming model.
—Chapter 22, “Integrated Security Engine (SEC),” provides an overview of the MCF548x
security encryption controller.
—Chapter 23, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of
the MCF548x JTAG test implementation. It describes the use of JTAG instructions and
provides information on how to disable JTAG functionality.
•Part IV, “Communications Subsystem,” contains chapters that discuss the operation and
configuration of the communications I/O subsystem including the MCF548x multichannel DMA,
communications timer, PSC, FEC, DSPI, and USB2, and I2C.
—Chapter 24, “Multichannel DMA,” provides an overview of the multichannel DMA controller
module including the operation of the external DMA request signals.
—Chapter 25, “Comm Timer Module (CTM),” contains a detailed description of the
communications timer module, which functions as a baud clock generator or as a DMA task
initiator.
—Chapter 26, “Programmable Serial Controller (PSC),” provides an overview of asynchronous,
synchronous, and IrDA 1.1 compliant receiver/transmitter serial communications of the
MCF548x.
—Chapter 27, “DMA Serial Peripheral Interface (DSPI),” describes the use of the DMA serial
peripheral interface (DSPI) implemented on the MCF548x processor, including details of the
DSPI data transfers. The chapter concludes with timing diagrams and the DSPI features that
support Tx and Rx FIFO queue management.
—Chapter 28, “I2C Interface,” describes the MCF548x I2C module, including I2C protocol,
clock synchronization, and the registers in the I2C programing model. It also provides
programming examples.
—Chapter 29, “USB 2.0 Device Controller,” provides an overview of the USB 2.0 device
controller module used in the MCF548x.
—Chapter 30, “Fast Ethernet Controller (FEC),” provides a feature-set overview, a functional
block diagram, and transceiver connection information for both MII (Media Independent
Interface) and 7-wire serial interfaces. It also provides describes operation and the
programming model.
•Part V, “Mechanical,” provides a pinout and both electrical and functional descriptions of the
MCF548x signals. It also describes how these signals interact to support the variety of bus
operations shown in timing diagrams.
—Chapter 31, “Mechanical Data,” provides a functional pin listing and package diagram for the
MCF548x.

Suggested Reading

This section lists additional reading that provides background for the information in this manual as well as
general information about the ColdFire architecture.