Freescale Semiconductor 3.9 Precise Faults

MCF548x Reference Manual, Rev. 3
3-42 Freescale Semiconductor
3.9 Precise Faults
To support a demand-paged virtual memory environment, all memory references require precise,
recoverable faults. The ColdFire instruction restart mechanism ensures that a faulted instruction restarts
from the beginning of execution; that is, no internal state information is saved when an exception occurs
and none is restored when the handler ends. Given the PC address defined in the exception stack frame,
the processor reestablishes program execution by transferring control to the given location as part of the
RTE (return from exception) instruction.
The instruction restart recovery model requires program-visible register changes made during execution
to be undone if that instruction subsequently faults.
The Version 4 (and later) OEP structure naturally supports this concept for most instructions;
program-visible registers are updated only in the final OEP stage when fault collection is complete. If any
type of exception occurs, pending register updates are discarded.
For V4 cores and later, most single-cycle instructions already support precise faults and instruction restart.
Some complex instructions do not. Consider the following memory-to-memory move:
mov.l (Ay)+,(Ax)+ # copy 4 bytes from source to destination
On a Version 4 processor, this instruction takes one cycle to read the source operand (Ay) and one to write
the data into Ax. Both the source and destination address pointers are updated as part of execution.
Table 3-24 lists the operations performed in execute stage (EX).
A fault detected with the destination memory write is reported during the second cycle. At this point,
operations performed in the first cycle are complete, so if the destination write takes any type of access
error, Ay is updated. After the access error handler executes and the faulting instruction restarts, the
processor’s operation is incorrect because the source address register has an incorrect (post-incremented)
value.
To recover the original state of the programming model for all instructions, the CF4e CPU adds the needed
hardware to support full register recovery. This hardware allows program-visible registers to be restored
to their original state for multi-cycle instructions so that the instruction restart mechanism is supported.
Memory-to-memory moves and move multiple loads are representative of the complex instructions
needing the special recovery support.
The other major pipeline change affects the IFP. The IFP and OEP are decoupled by a FIFO instruction
buffer. In the V4 IFP, each buffer entry includes 48 bits of instruction data fetched from memory and 64
bits of early decode and branch prediction information. This datapath is expanded slightly to include IFP
fault status information. Thus, every IFP access can be tagged in case an instruction fetch terminates with
an error acknowledge.
Table 3-24. OEP EX Cycle Operations
EX Cycle Operations
1 Read source operand from memory @ (Ay), update Ay, new Ay = old Ay + 4
2 Write operand into destination memory @ (Ax), update Ax, new Ax = old Ax + 4, update CCR