MCF548x Reference Manual, Rev. 3
xlii Freescale Semiconductor
—Chapter 7, “Local Memory,” describes the MCF548x implementation of the ColdFire V4e
local memory specification.
—Chapter 8, “Debug Support,” describes the Revision C enhanced hardware debug support in the
MCF548x. This revision of the ColdFire debug architecture encompasses earlier revisions.
•Part II, “System Integration Unit,” describes the system integration unit, which provides overall
control of the bus and serves as the interface between the ColdFire core processor complex and
internal peripheral devices. It includes a general description of the SIU and individual chapters that
describe components of the SIU, such as the interrupt controller, general purpose timers, slice
timers, and GPIOs. Part II contains the following chapters:
—Chapter 9, “System Integration Unit (SIU),” describes the SIU programming model, bus
arbitration, and system-protection functions for the MCF548x.
—Chapter 10, “Internal Clocks and Bus Architecture,” describes the clocking and internal buses
of the MCF548x and discusses the main functional blocks controlling the XL bus and the XL
bus arbiter.
—Chapter 11, “General Purpose Timers (GPT),” describes the functionality of the four general
purpose timers, GPT0–GPT3.
—Chapter 12, “Slice Timers (SLT),” describes the two slice timers, shorter term periodic
interrupts, used in the MCF548x.
—Chapter 13, “Interrupt Controller,” describes operation of the interrupt controller portion of the
SIU. Includes descriptions of the registers in the interrupt controller memory map and the
interrupt priority scheme.
—Chapter 14, “Edge Port Module (EPORT),” describes EPORT module functionality.
—Chapter 15, “GPIO,” describes the operation and programming model of the parallel port pin
assignment, direction-control, and data registers.
•Part III, “On-Chip Integration,” describes the on-chip integration for the MCF548x device. It
includes descriptions of the system SRAM, FlexBus interface, SDRAM controller, PCI, and SEC
cryptography accelerator. Part III contains the following chapters:
—Chapter 16, “32-Kbyte System SRAM,” describes the MCF548x on-chip system SRAM
implementation. It covers general operations, configuration, and initialization.
—Chapter 17, “FlexBus,” describes data transfer operations, error conditions, and reset
operations. It describes transfers initiated by the MCF548x and by an external master, and
includes detailed timing diagrams showing the interaction of signals in supported bus
operations.
—Chapter 18, “SDRAM Controller (SDRAMC),” describes configuration and operation of the
synchronous DRAM controller component of the SIU. It includes a description of signals
involved in DRAM operations, including chip select signals and their address, mask, and
control registers.
—Chapter 19, “PCI Bus Controller,” details the operation of the PCI bus controller for the
MCF548x.
—Chapter 20, “PCI Bus Arbiter Module,” describes the MCF548x PCI bus arbiter module,
including timing for request and grant handshaking, the arbitration process, and the register in
the PCI bus arbiter programing model.