Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 26-43
.

26.4.9 PSC FIFO System

The receive FIFO stack consists of the FIFO and a receiver shift register connected to the RxD. Data is
assembled in the receiver shift register and loaded into the FIFO at the location pointed to by the FIFO
write pointer.
Reading the Rx buffer produces an output of data from the location pointed to by the FIFO read pointer.
After the read cycle, data at the top of the FIFO stack is popped and the Rx shift register can add new data
at the bottom of the FIFO. The standard FIFO controller used in MCF548x peripherals, such as the PSCs,
was designed to control either a transmit (Tx) or a receive (Rx) FIFO
Depending on whether the FIFO is set for Tx or Rx, alarm and granularity are measured differently, either:
• valid data bytes (Tx FIFO)
• empty bytes (Rx FIFO)
For both Tx and Rx FIFOs:
• Alarm specifies a threshold at which the FIFO generates an interrupt to either:
— Multichannel DMA
— CPU (alternate)
• Granularity specifies a threshold at which the interrupt goes away.
Each PSC provides two control lines to the Multichannel DMA system, control the transfer from and to
the PSC FIFO. The FIFOs can be accessed as follows:
• 8-bit codec mode or UART mode
— Can access FIFOs either 1, 2, or 4 one-byte samples at a time.
• 16-bit codec mode:
— Can access FIFOs 1 or 2 two-byte samples at a time.
• 32-bit and 32-bit codec mode
— Can access FIFOs four-byte samples at a time
• AC97 mode:
— Must access FIFOs one sample at a time
— In addition, when the Rx FIFO is being read, a “1” in bit 20 (21st bit of the sample) marks this
sample as the first time slot of a new frame.
Block error mode is always selected because PSCMR1n[ERR] is hard-wired high. In block mode PSCSRn
shows a logical OR of all characters received after the last RESET ERROR STATUS command. Block mode
offers a data-reception speed advantage where the software overhead of error-checking each character
cannot be tolerated. Errors are not detected until the check is done at the end of an entire message; the
faulting character is not identified.
Reading PSCSRn does not affect the FIFO. The FIFO is popped only when the Rx buffer is read. If the Rx
FIFO is completely full, a new character is held in the Rx shift register until space is available. However,
if a second new character is received, contents of the character in the Rx shift register is lost. The FIFOs
Table 26-38. Chip Patterns for FIR Fields
PA 1000 0000 1010 1000 (16 times repeated)
STA 0000 1100 0000 1100 0110 0000 0110 0000
STO 0000 1100 0000 1100 0000 0110 0000 0110
first chip last chip