MCF548x Reference Manual, Rev. 3
24-28 Freescale Semiconductor
4. Priority registers - These will typically only be set during initialization, but can be changed during
operation if desired.
5. Initiator Mux Control register - This will typically be set up during configuration and will be
dependent on what modules of the chip which the system is using.
6. Task Size registers - The Task Size registers may or may not need to be initialized. These registers
may not be used by a task if the task has hardcoded what transfer sizes to use in its DRDs. If the
task will use the same task descriptor table every time it is enabled, then these registers may only
need to be initialized once. If a different task descriptor is used, these registers may need to be set
before each time the task is enabled.
7. Task Control registers - These registers must be programmed to enable the task.

24.5.2 Task Memory

DMA task memory is comprised of the task table, task descriptor tables, variable tables, function
descriptor tables and context save spaces. These memory areas are described briefly in Section 24.3.1,
“DMA Task Memory.” Each of these areas must be set up in user provided memory such as the internal
system SRAM or DRAM. The task table is programmed with information which allows the DMA to locate
these areas of memory and also with control information for each task.
This process can be handled by using the software API . Please refer to the “Multichannel DMA API
User’s Guide” for more information on the API interface used for the MCF548x family.
The microcode can be executed from various memory areas accessible by the DMA such as SDRAM,
memory on the FlexBus, or the internal SRAM. It is recommended that the DMA task memory be located
in SRAM because of improced performance.
The major components of the task table are described in the next section.

24.5.2.1 Task Table

The task table, whose format is shown in Figure 24-23, should reside at the address specified by TaskBAR.
The task table base address must be aligned to a 512-byte boundary. There are sixteen tasks, each of which
has its own unique task descriptor table (TDT) start pointer, TDT end pointer, variable table pointer,
control information, and status information. The TDT start pointer is a 32-bit value that points to the first
loop control descriptor, or LCD, of that particular task. The remaining descriptors [both LCDs and data
routing descriptors (DRDs)] should consecutively follow the first one in memory, except in special
branching cases. The TDT end pointer is a 32-bit value that points to the last descriptor, which must be a
DRD, of that particular task.
The 32-bit variable table pointer points to the top of the 48-longword (192-byte) memory space where this
task’s variable table resides. As previously mentioned, this table may be reduced to 128 bytes if none of
the last 16 variables are used. Before executing a particular task, that task’s variable table must be
initialized with the appropriate data.
The function descriptor base address points to the location of the function descriptors used for the various
execution units (EUs). For each EU, there are 16 available function descriptors. The function descriptor
base address pointer is only 24 bits, which function as the 24 most significant bits of a 32 bit address.
Therefore, the function descriptor table must be aligned on a 256-byte boundary.
The control information for each task is located in the fourth longword of the task table as shown in
Figure 24-23. Control bits 7 through 0 are for precise increment, save all registers, integer mode,
speculative prefetch, read line, and combine writes.