MCF548x External Signals
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 2-19
2.2.2.3 SDRAM Bank Addresses (SDBA[1:0])
Each SDRAM module has four internal row banks. The SDBA[1:0] signals are used to select the row bank.
It is also used to select the SDRAM internal mode register during power-up initialization.
2.2.2.4 SDRAM Row Address Strobe (RAS)
This output is the SDRAM synchronous row address strobe.
2.2.2.5 SDRAM Column Address Strobe (CAS)
This output is the SDRAM synchronous column address strobe.
2.2.2.6 SDRAM Chip Selects (SDCS[3:0])
These signals interface to the chip select lines of the SDRAMs within a memory block. Thus, there is one
SDCS line for each memory block (the MCF548x supports up to four SDRAM memory blocks).
2.2.2.7 SDRAM Write Data Byte Mask (SDDM[3:0])
These output signals are sampled by the SDRAM on both edges of SDDQS to determine which byte lanes
of the SDRAM data bus should be latched during a write cycle. In DDR mode, these bits are ignored during
read operations.
2.2.2.8 SDRAM Data Strobe (SDDQS[3:0])
These bidirectional signals indicate when valid data is on the SDRAM data bus when in DDR mode.
2.2.2.9 SDRAM Clock (SDCLK[1:0])
These signals are the output clock for SDRAM cycles.
2.2.2.10 Inverted SDRAM Clock (SDCLK[1:0])
These signals are the inverted version of the SDRAM clock. They are used with SDCLK to provide the
differential clocks for DDR SDRAM.
2.2.2.11 SDRAM Write Enable (SDWE)
The SDRAM write enable (SDWE) is asserted to signify that an SDRAM write cycle is underway. A read
cycle is indicated by the negation of SDWE.
2.2.2.12 SDRAM Clock Enable (SDCKE)
This output is the SDRAM clock enable. SDCKE is negated to put the SDRAM into low-power,
self-refresh mode.
2.2.2.13 SDR SDRAM Data Strobe (SDRDQS)
This signal is connected to SDDQS inputs. It is used in SDR mode only.