Freescale Semiconductor 10.3 XL Bus Arbiter

MCF548x Reference Manual, Rev. 3
10-6 Freescale Semiconductor
10.3 XL Bus Arbiter
The XL bus arbiter handles bus arbitration between XL bus masters.
10.3.1 Features
The arbiter features are as follows:
• Eight priority levels
• Priority levels may be changed dynamically by XL bus masters
• XL bus arbitration support for eight masters
• Least recently used (LRU) priority scheme for masters of equal priority
• Multiple masters at each priority level supported
• One level of address pipelines is enforced by the arbiter
• Bus grant parking modes:
— No parking
— Park on last master
— Park on programmed master
• Watchdog timers for various XL bus time-out conditions
10.3.2 Arbiter Functional Description
10.3.2.1 Prioritization
The prioritization function will indicate that a master is requesting the bus and indicate which master has
priority.
Priority is determined first by using the hardcoded master priority or the master n priority bits in the arbiter
master priority register (XARB_PRIEN), depending on the arbiter master priority enable bit for each
master. Secondly, masters at the same level of priority will be further sorted by a least recently used
9 PSCEN PSC Clock Enable - Controls clock for all PSC modules.
8 — Reserved, should be cleared.
7 USBEN USB Clock Enable
6 FEC1EN FEC1 Clock Enable
5 FEC0EN FEC0 Clock Enable
4 DMAEN Multi-channel DMA Clock Enable
3 CAN0EN CAN0 Clock Enable
2 FBEN FlexBus Clock Enable
1 PCIEN PCI Bus Clock Enable
0 MEMEN Memory Clock Enable - Controls clocks of the SDRAM controller module
Table 10-3. SPCR Field Descriptions (Continued)
Bits Name Description