Freescale Semiconductor Figure 17-31 illustrates a write burst transfer with one wait state., Figure 17-34 shows a write cycle with one clock of address setup and address hold.

MCF548x Reference Manual, Rev. 3
17-30 Freescale Semiconductor
Figure 17-31 illustrates a write burst transfer with one wait state.
Figure 17-32. Longword Write Burst to 8-Bit Port 4-2-2-2 (One Wait State)
If address setup and hold are used, only the first and last beat of the burst cycle will be affected as shown
in Figure 17-33.
Figure 17-33. Longword Read Burst from 8-Bit Port 4-1-1-1 (Address Setup and Hold)
Figure 17-34 shows a write cycle with one clock of address setup and address hold.
CLK
AD[23:0]
AD[31:24]
R/W
ALE
TA
OE
S0 S1 WS S2 WS/SWS S2 WS/SWS S2 WS/SWS S2 S3
FBCSn, BE/BWEn
ADDR[23:0]
A[31:24]
DATA
TSIZ[1:0] 00
TBST
DATA DATA
DATA
CLK
AD[23:0]
AD[31:24]
R/W
ALE
TSIZ[1:0]
TA
TBST
S0 AS S1 S2 S2 S2 S2 S3 AH
OE
ADDR[23:0]
A[31:24] DATA DATA DATA DATA
FBCSn, BE/BWEn
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