Cache Operation
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 7-11
pseudo-round-robin replacement algorithm to choose the line to be deallocated and replaced. First the
cache controller looks for an invalid line, with way 0 the highest priority. If all lines have valid data, a 2-bit
replacement counter is used to choose the way. After a line is allocated, the pointer increments to point to
the next way.
Cache lines from ways 0 and 1 can be protected from deallocation by enabling half-cache locking. If
CACR[DHLCK,IHLCK] = 1, the replacement pointer is restricted to way 2 or 3.
As part of deallocation, a valid, unmodified cache line is invalidated. It is consistent with system memory,
so memory does not need to be updated. To deallocate a modified cache line, data is placed in a push buffer
(for an external cache line push) before being invalidated. After invalidation, the new entry can replace it.
The old cache line may be written after the new line is read.
When a cache line is selected to host a new cache entry, the following three things happen:
1. The new address tag bits A[31:13] are written to the tag.
2. The cache line is updated with the new memory data.
3. The cache line status changes to a valid state (V = 1).
Read cycles that miss in the cache allocate normally as previously described.
Write cycles that miss in the cache do not allocate on a cacheable write-through region, but do allocate for
addresses in a cacheable copyback region.
A copyback byte, word, longword, or line write miss causes the following:
1. The cache initiates a line fill or flush.
2. Space is allocated for a new line.
3. V and M are both set to indicate valid and modified.
4. Data is written in the allocated space. No write to memory occurs.
Note the following:
• Read hits cannot change the status bits and no deallocation or replacement occurs; the data or
instructions are read from the cache.
• If the cache hits on a write access, data is written to the appropriate portion of the accessed cache
line. Write hits in cacheable, write-through regions generate an external write cycle and the cache
line is marked valid, but is never marked modified. Write hits in cacheable copyback regions do
not perform an external write cycle; the cache line is marked valid and modified (V = 1 and M = 1).
• Misaligned accesses are broken into at least two cache accesses.
• Validity is provided only on a line basis. Unless a whole line is loaded on a cache miss, the cache
controller does not validate data in the cache line.
Write accesses designated as cache-inhibited by the CACR or ACR bypass the cache and perform a
corresponding external write.
Normally, cache-inhibited reads bypass the cache and are performed on the external bus. The exception to
this normal operation occurs when all of the following conditions are true during a cache-inhibited read:
• The cache-inhibited fill buffer bit, CACR[DNFB], is set.
• The access is an instruction read.
• The access is normal (that is, transfer type (TT) equals 0).
In this case, an entire line is fetched and stored in the fill buffer. It remains valid there, and the cache can
service additional read accesses from this buffer until either another fill or a cache-invalidate-all operation
occurs.