Freescale Semiconductor 7.9.3 Cache Coherency (Data Cache Only), 7.9.4 Memory Accesses for Cache Maintenance

Cache Operation
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 7-15
7.9.2.3 Read Hit
On a read hit, the cache provides the data to the processor core and the cache line state remains unchanged.
If the cache mode changes for a specific region of address space, lines in the cache corresponding to that
region that contain modified data are not pushed out to memory when a read hit occurs within that line.
First execute a CPUSHL instruction or set CACR[DCINVA,ICINVA] before switching the cache mode.
7.9.2.4 Write Hit (Data Cache Only)
The cache controller handles processor writes that hit in the data cache differently for write-through and
copyback regions. For write hits to a write-through region, portions of cache lines corresponding to the
size of the access are updated with the data. The data is also written to external memory. The cache line
state is unchanged. For copyback accesses, the cache controller updates the cache line and sets the M bit
for the line. An external write is not performed and the cache line state changes to (or remains in) the
modified state.
7.9.3 Cache Coherency (Data Cache Only)
The MCF548x provides limited cache coherency support in multiple-master environments. Both
write-through and copyback memory update techniques are supported to maintain coherency between the
cache and memory.
The cache does not support snooping (that is, cache coherency is not supported while external or DMA
masters are using the bus). Therefore, on-chip DMAs of the MCF548x cannot access local memory and
do not maintain coherency with the data cache.
7.9.4 Memory Accesses for Cache Maintenance
The cache controller performs all maintenance activities that supply data from the cache to the core,
including requests to the SIU for reading new cache lines and writing modified lines to memory. The
following sections describe memory accesses resulting from cache fill and push operations. Chapter 17,
“FlexBus,” describes required bus cycles in detail.
7.9.4.1 Cache Filling
When a new cache line is required, a line read is requested from the SIU, which generates a burst-read
transfer by indicating a line access with the size signals, SIZ[1:0].
The responding device supplies 4 consecutive longwords of data. Burst operations can be inhibited or
enabled through the burst read/write enable bits (BSTR/BSTW) in the chip-select control registers
(CSCR0–CSCR7).
SIU line accesses implicitly request burst-mode operations from memory. For more information regarding
external bus burst-mode accesses, see Chapter 17, “FlexBus.”
The first cycle of a cache-line read loads the longword entry corresponding to the requested address.
Subsequent transfers load the remaining longword entries.
A burst operation is aborted by an a write-protection fault, which is the only possible access error.
Exception processing proceeds immediately. Note that unlike Version 2 and Version 3 access errors, the
program counter stored on the exception stack frame points to the faulting instruction. See Section 3.8.2,
“Processor Exceptions.”