Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-35

Table 30-34. FECTFSR Field Descriptions

Bits Name Descriptions
31 IP Illegal pointer. This bit signifies an illegal pointer condition in the FIFO controller. For example, if a
value larger than the FIFO controller’s memory range is written to a Read, Write, Last Read, or Last
Write Pointer, the IP bit will assert. If not masked, a one in this bit will cause a XFERR in the EIR.
This bit will remain set until a one is written to this bit location.
0 No illegal pointer condition.
1 An address outside the FIFO controller’s memory range has been written to one of the user-visible
pointers.
This bit should always be 0 on the FEC since the transmit FIFO size is fixed.
30 TXW Transmit Wait Condition - STICKY, WRITE TO CLEAR
This bit indicates that the ipf_xmit bus is incurring wait states because there is not enough data in
the FIFO to satisfy the read request without causing underflow. This bit will cause the error outputs
to assert unless the TXW_MASK bit in the FIFO Control register is set. This bit will remain set until
a 1 is written to this bit location
27–24 FRM Frame indicator. Read-only. This bus provides a frame status indicator for non-DMA applications.
1000 A frame boundary has occurred on the [31:24] byte of the data bus
0100 A frame boundary has occurred on the [23:16] byte of the data bus
0010 A frame boundary has occurred on the [15:8] byte of the data bus
0001 A frame boundary has occurred on the [7:0] byte of the data bus
23 FAE Frame accept error. This bit indicates a frame accept error in the FIFO controller and will set if the
user has over-written data in a transmit FIFO for a frame that needs to be retried. If not masked, a
one in this bit will cause a XFERR in the EIR. This bit will remain set until a one is written to this bit
location. This bit is inactive when the FIFO is not programmed for frame mode.
0 No frame accept error.
1 Frame accept error.
22 — Reserved, should be cleared.
21 UF FIFO underflow. This bit signifies the read pointer has surpassed the write pointer. If not masked, a
one in this bit will cause a XFERR in the EIR. This bit will remain set until a 1 is written to this bit
location. This bit will not assert if the FEC overreads the FIFO because the FIFO will insert wait
states to the FEC. For notification of transmit underflow, see EIR[XFUN].
20 OF FIFO overflow. This bit signifies the write pointer has surpassed the read pointer. If not masked, a
one in this bit will cause a XFERR in the EIR. This bit will remain set until a 1 is written to this bit
location.
19 FRMRDY Frame ready. This read only bit indicates that there is framed data ready. All complete frames must
be read from the FIFO to clear this bit. This bit will only be set while in frame mode.
18 FU Full. This read only bit indicates that the FIFO is full. The FIFO must be read to clear this bit.
17 ALARM Alarm. This read only bit indicates that the FIFO has determined an alarm condition.When the FIFO
is configured to transmit, the FIFO alarm provides low level indication, setting when there are less
than or equal alarm bytes in the FIFO (see Section 30.3.3.27, “FEC Transmit FIFO Status Register
(FECTFSR),” for more information). The alarm is cleared when the FIFO is written so that less than
( 4 × FECTFCR[GR]) free bytes in the FIFO.
16 EMT Empty. This read only bit indicates that the FIFO is empty. The FIFO must be written to clear this bit.
15–0 — Reserved, should be cleared.