Freescale Semiconductor 24.6.3 Pipelined Requests

Timing Diagrams
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 24-31
DACKto assert (clock 5). The next falling edge of DREQ occurs during clock 8, causing the internal
request to assert on the rising edge of clock 9.
Figure 24-25. Edge-Triggered External Request Timing
24.6.3 Pipelined Requests
Figure 24-26 shows the timing for pipelined external requests. For pipelined requests, the internal DMA
request will assert when there is a falling edge of the DREQ signal and the previous transfer has been
completed (DACK low). DREQ goes low during clock 1. In edge-triggered mode, this would cause the
internal request to assert on the rising edge of clock 2. However, in pipelined mode the internal request
waits for the previous transfer to be acknowledged (clock 2) before the internal request is asserted on the
rising edge of clock 3. The transfer is completed and acknowledge internally during clock 5 causing
DACK to assert during clock 6. Since the transfer has already been acknowledged, the next falling edge
of DREQ (during clock 7) causes the assertion of the internal request of the following rising clock edge
(clock 8). Note that DACK is not deasserted until the new internal request asserts.
Figure 24-26. Pipelined External Requests
123456789100
CLK
DREQ
DACK
Internal DMA
Request
Internal DMA
Acknowledge
123456789100
CLK
DREQ
DACK
Internal DMA
Request
Internal DMA
Acknowledge