Cache Organization
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 7-7
The MCF548x processor’s Harvard memory structure includes a 32-Kbyte data cache and a 32-Kbyte
instruction cache. Both are nonblocking and 4-way set-associative with a 16-byte line. The cache improves
system performance by providing single-cycle access to the instruction and data pipelines. This decouples
processor performance from system memory performance, increasing bus availability for on-chip DMA
or external devices. Figure 7-2 shows the organization and integration of the data cache.
Figure 7-2. Data Cache Organization
Both caches implement line-fill buffers to optimize line-sized burst accesses. The data cache supports
operation of copyback, write-through, or cache-inhibited modes. A four-entry, 32-bit buffer supports cache
line-push operations, and can be configured to defer write buffering in write-through or cache-inhibited
modes. The cache lock feature can be used to guarantee deterministic response for critical code or data
areas.
A nonblocking cache services read hits or write hits from the processor while a fill (caused by a cache
allocation) is in progress. As Figure 7-2 shows, accesses use a single bus connected to the cache.
All addresses from the processor to the cache are physical addresses. A cache hit occurs when an address
matches a cache entry. For a read, the cache supplies data to the processor. For a write, which is permitted
only to the data cache, the processor updates the cache. If an access does not match a cache entry (misses
the cache) or if a write access must be written through to memory, the cache performs a bus cycle on the
internal bus and correspondingly on the external bus by way of the system integration unit (SIU).
The cache module does not implement bus snooping; cache coherency with other possible bus masters
must be maintained in software.

7.8 Cache Organization

A four-way set associative cache is organized as four ways (levels). There are 512 sets in the 32-Kbyte
data cache with each line containing 16 bytes (4 longwords). The 32-Kbyte instruction cache has 512 sets.
Entire cache lines are loaded from memory by burst-mode accesses that cache 4 longwords of data or
instructions. All 4 longwords must be loaded for the cache line to be valid.
Figure 7-3 shows data cache organization as well as terminology used.
System
Address/
Control
Cache
Control Logic
Directory Array
Data Array
Data Path
ColdFire
Address Path
Control
Data
Address
External
Bus
Data
Control
Data
Address
Integration
Unit
(SIU)
Processor
Core