Freescale Semiconductor 27.7.3 DSPI Baud Rate and Clock Delay Generation

MCF548x Reference Manual, Rev. 3
27-22 Freescale Semiconductor
27.7.2.5 Rx FIFO Buffering Mechanism
The Rx FIFO functions as a buffer for data received on the DSPISIN signal. The Rx FIFO holds from 1 to
16 received SPI data frames. SPI data is added to the Rx FIFO at the completion of a transfer when the
received data in the shift register is transferred into the Rx FIFO. SPI data is removed (popped) from the
Rx FIFO by reading the DRFR. Rx FIFO entries can only be removed from the Rx FIFO by reading the
DRFR or by flushing the Rx FIFO.
The Rx FIFO counter field (DSR[RXCTR]) indicates the number of valid entries in the Rx FIFO. The
RXCTR is updated every time the DRFR is read or when SPI data is copied from the shift register to the
Rx FIFO.
The DSR[RXPTR] field points to the Rx FIFO entry that is returned when the DRFR is read. The RXPTR
contains the positive offset from DRFDR0 in the number of 32-bit registers. For example, RXPTR equal
to two means that the DRFDR2 contains the received SPI data that will be returned when DRFR is read.
The RXPTR field is incremented every time the DRFR is read.
27.7.2.5.1 Filling the Rx FIFO
The Rx FIFO is filled with the received SPI data from the shift register. While the Rx FIFO is not full, SPI
frames from the shift register are transferred to the Rx FIFO. Every time an SPI frame is transferred to the
Rx FIFO, the Rx FIFO counter is incremented by one.
If the Rx FIFO and shift register are full and a transfer is initiated, the DSR[RFOF] bit is set indicating an
overflow condition. Depending on the state of the DMCR[ROOE] bit, the data from the transfer that
generated the overflow is either ignored or shifted into the shift register. If the ROOE bit is set, the
incoming data is shifted into the shift register and data is overwritten. If the ROOE bit is cleared, the
incoming data is ignored.
27.7.2.5.2 Draining the Rx FIFO
Host software or the DMA controller can remove (pop) entries from the Rx FIFO by reading the DRFR.
A read of the DRFR decrements the Rx FIFO counter by one. Attempts to pop data from an empty Rx FIFO
are ignored, the Rx FIFO counter remains unchanged. The data returned from reading an empty Rx FIFO
is undetermined.
When the Rx FIFO is not empty, the Rx FIFO drain flag (DSR[RFDF]) is set. The RFDF bit is cleared
when the Rx FIFO is empty and the DMA controller indicates that a read from DRFR is complete or by
host software writing a ‘1’ to the RFDF.
27.7.3 DSPI Baud Rate and Clock Delay Generation
The DSPISCK frequency and the delay values for serial transfer are generated by dividing the system
clock frequency by a prescaler and a scaler. Figure 27-13 shows conceptually how the DSPISCK signal is
generated. For the MCF548x, the clock rate is 100 MHz.
Figure 27-13. Communications Clock Prescalers and Scalers
DSPISCK
System Clock Prescaler
1
Scaler
1