Agilent Technologies 16760A manual Requirements Signal Timing Burst Transfers, 123

Requirements

Signal Timing - Burst Transfers

Chapter 4: Using the Logic Analyzer in Eye Scan Mode

Setting Up and Running Eye Scan Measurements

memory device versus a memory controller.

Qualified eye scans are performed with double edge clocks.

Qualified eye scans are available only in the 800 Mb/s mode of the 16760 logic analyzer.

When the qualifier is in use, there are six channels on the master card that cannot be measured by eye scan:

Pod 2, clock input (clock K) - the qualifier

Pod 2, channels 14 and 15

Pod 1, channels 0, 1, and 2

This limitation is due to the internal architecture of the analyzer.

You can not perform an eye scan on the J clock of the master logic analyzer card because this is the target system clock signal. It is used as the reference signal for the eye scan.

The qualifier feature is designed for systems using double data rate bursted transfers. In these systems, data is transferred on each edge of the clock. In other words, there are two data transfers for each clock cycle - one on the rising edge and one on the falling edge. Figure 1 shows a burst with four clock cycles and eight data transfers. The clock cycle begins on the rising edge of the clock.

The direction of the transfer (read versus write) is typically set up via an earlier command sequence (not shown).

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