Agilent Technologies 16760A manual Understanding State Mode Sampling Positions, 256

Chapter 6: Concepts

Understanding State Mode Sampling Positions

Understanding State Mode Sampling Positions

Synchronous sampling (state mode) logic analyzers are like edge- triggered flip-flops in that they require input logic signals to be stable for a period of time before the clock event (setup time) and after the clock event (hold time) in order to properly interpret the logic level. The combined setup and hold time is known as the setup/hold window.

A device under test (because of its own setup/hold requirements) specifies that data be valid on a bus for a certain length of time. This is known as the data valid window. The data valid window on most buses is generally less than half of the bus clock period.

To accurately capture data on a bus:

•The logic analyzer's setup/hold time must fit within the data valid window.

•Because the location of the data valid window relative to the bus clock is different for different types of buses, the position of the logic analyzer's setup/hold window must be adjustable (relative to the sampling clock, and with fine resolution) within the data valid window. For example:

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