Chapter 2: Probing and Selecting the Sampling Mode

Choosing the Sampling Mode

Choosing the Sampling Mode

There are three logic analyzer sampling modes to choose from: timing mode, state mode, or eye scan mode.

In timing mode, the logic analyzer samples asynchronously, based on an internally-generated sampling clock.

In state mode, the logic analyzer samples synchronously, based on a sampling clock signal (or signals) from the device under test. Typically, the signal used for sampling in state mode is a state machine or microprocessor clock signal.

In eye scan mode, the logic analyzer samples small windows of time and voltage on data channels around a clock signal from the device under test. The resulting eye diagrams let you validate and characterize the data valid windows of the signals on a bus.

“Selecting the Timing Mode (Asynchronous Sampling)” on page 43

“Selecting the State Mode (Synchronous Sampling)” on page 46

“In Either Timing Mode or State Mode” on page 53

“Selecting the Eye Scan Mode” on page 55

Selecting the Timing Mode (Asynchronous Sampling)

In timing mode, the logic analyzer samples asynchronously, based on an internally-generated sampling clock.

“To select the timing mode” on page 44

“To select the conventional/transitional configuration” on page 44

“To specify the sample period” on page 45

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Agilent Technologies 16760A manual Choosing the Sampling Mode, Selecting the Timing Mode Asynchronous Sampling