Agilent Technologies 16760A manual Clock cycle of the next burst, Are supported, 125

Chapter 4: Using the Logic Analyzer in Eye Scan Mode

Setting Up and Running Eye Scan Measurements

	The qualifier is changed on the second clock cycle of the burst. It
	remains stable until after the next clock cycle following the end of the
	burst. If the clock pauses between bursts (as shown above), then the
	qualifier level for the previous burst remains in place until the second
	clock cycle of the next burst.
	If the clock free-runs between bursts, then the qualifier should be
	taken false on the cycle following the end of the burst, and returned
	true on the second cycle of the next burst (if that burst is to be
	qualified for eye scan). If each burst is only one clock cycle (two data
	transfers), then the qualifier will be changing on the first edge of each
	burst, but the level will be for the previous burst. Variable size bursts
	are supported.
NOTE:	If you have more than one logic analyzer card, the following procedure applies
	to the master card. The master card is the one that receives the clock signal
	from the target system on its J clock input.
Procedure	First, set up the sampling position for the qualifier
	1. Connect the qualification signal from your target system to the Pod A2
	clock (the K clock) input of the master logic analyzer card.
	2. On the Sampling tab, select the State Mode button, and select 800 Mb/s
	acquisition mode.

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