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Chapter 2: Probing and Selecting the Sampling Mode
Choosing the Sampling Mode
To select the state mode1. Open the logic analyzer Setup window.
2. Select the Sampling tab.
3. Choose the State Mode option.
You can also select the state sampling mode in the “Pod Assignment
Dialog” on page 175.
To select the state speed configuration1. In the Sampling tab, with State Mode selected, select one of the state
analyzer configurations.
The selected configuration specifies the speed up to whi ch the state mode
sampling clock will match input clock edges from the device under test.
For example, in the 800 Mb/s / 64M State configuration, the state mode
sampling clock will match input clock edges up to 800 MHz.
The selected configuration also specifies the memory depth for samples
and whether only half of the logic analyzer channels are available.
You can choose from:
• 1500 Mb/s / 128M Half Channel
In this configuration: The input clock signal must be periodic, and both
edges indicate valid data. The clock input can only be used as a clock
and not as an extra data channel. The logic analyzer setup/hold window
is 500 ps, and eye finder must be used to automatically adj ust
sampling positions. The limited set of 1 6760 Half Channel State
trigger functions are available. In half-channel mode the analyzer
accesses only the even channels (0, 2, 4, etc.).
• 1250 Mb/s / 128M Half Channel
In this configuration: The input clock signal must be periodic, and both
edges indicate valid data. The clock input can only be used as a clock
and not as an extra data channel. The logic analyzer setup/hold window
is 1 ns, and sampling positions may be adjusted automatically or
manually. The limited set of 16760 Half Channel State trigger
functions are available. In half-channel mode the analyzer accesses
only the even channels (0, 2, 4, etc.).