Agilent Technologies 16760A manual Selecting the State Mode Synchronous Sampling

Chapter 2: Probing and Selecting the Sampling Mode

Choosing the Sampling Mode

State Mode Sampling Position

Selecting the State Mode (Synchronous

Sampling)

In state mode, the logic analyzer samples synchronously, based on a sampling clock signal from the device under test. Typically, the signal used for sampling in state mode is a state machine or microprocessor clock signal.

The clock signal can be either Periodic (synchronous all the time), or Aperiodic (bursted or varying in frequency).

•“To select the state mode” on page 47

•“To select the state speed configuration” on page 47

•“To set up the sampling clock” on page 48

In order for a state mode logic analyzer to accurately capture data from a device under test, the logic analyzer's setup/hold time (window) must fit within the device under test's data valid window.

Because the location of the data valid window relative to the bus clock is different for different types of buses, the logic analyzer lets you adjust the sampling position in order to accurately capture data on high-speed buses (see “Understanding State Mode Sampling Positions” on page 256).

When the device under test's data valid window is less than 2.5 ns (roughly, for clock speeds >= 200 MHz), it's easiest to use eye finder to locate the stable and transitioning regions of signals and to automatically adjust sampling positions.

•“To automatically adjust sampling positions” on page 49

When the device under test's data valid window is greater than 2.5 ns (roughly, for clock speeds < 200 MHz), it's easiest to adjust the sampling position manually, without using the logic analyzer to locate the stable and transitioning regions of signals.

•“To manually adjust sampling positions” on page 52

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